On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

Abstract

High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV 2 /R on,sp is similar. By using a high-K dielectric in the shallow trench isolation (STI) to further enhance the dielectric RESURF, the BV is increased and the R on,sp is reduced, yielding a significantly improved BV 2 /R on,sp , together with a better ON/OFF current ratio. However, with the insertion of the high-K STI, C GD is increased and a punch-through in the drift region caused by the depletion region occurs at a smaller V DS , which is consistent with theory. It is observed that the high-K dielectric RESURF also has an impact on the vertical breakdown, and care must be taken to achieve an optimal BV. The simulation results presented in this paper are of great importance for realizing a system-on-a-chip (SOC) based on advanced CMOS technologies.

Bottom-up vertical GaN nanocolumn Schottky barrier diodes with extremely high packing density grown by molecular beam epitaxy

“…As mentioned in the introduction, nanocolumn structures with embedded dielectric exhibit the dielectric RESERF effect. Here, as materials with higher permittivity of the embedded dielectric tend to be more effective, 27) we have embedded relatively high permittivity Al 2 O 3 using ALD in this study. However, it is crucial to ensure proper embedding for the expected effect to be fully realized.…”

A drain extended FinFET with enhanced DC/RF performance for high-voltage RF applications

“…Based on their excellent properties, FinFETs have also attracted great attention in system-on-a-chip (SoC) technology [5,6]. A FinFET design suitable for SoC technology has been actively pursued, and related studies are underway [7][8][9][10]. Most of these studies aim at realizing a high-voltage device based on the FinFET with a lower leakage current, lower hot carrier injection, and higher breakdown voltage (V BD ) [6].…”

“…In particular, a short L ch is required for these high-voltage FinFETs to meet the scaling trend of the SoC technology [11]. The conventional high-voltage FinFETs mostly adopt a drain extension (DE) structure, often called DeFinFET [7][8][9][10]. The lightly doped DE region mitigates the channel-DE junction's maximum electric field by distributing the potential throughout the DE region.…”

“…The DF-DeFF achieves a 4.3% higher peak f T of 114.2 GHz than the C-DeFF of 109.5 GHz.Although the DF-DeFF significantly improves g m by about 26%, f T is slightly increased. This is because the parasitic C gd increases due to the high-k FP[9]. As described in equation (1), the increased C gd results in a decreased f T .…”