On the electrical SOA of integrated vertical DMOS transistors

Moens, P.; Reynders, K.

doi:10.1109/led.2005.845497

Cited by 11 publications

(4 citation statements)

References 4 publications

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“…The drain current increases slightly before it saturates again at a region known as the safeoperating-area (SOA) of the high-voltage device [8,9]. Another special characteristic exhibited by HV-LDMOSs is the RESURF effect where the lightly doped n-drift region reduces the potential crowding under the field-oxide layer allowing higher breakdown voltages [10]. Hence the model should exhibit the quasi-saturation effect and RESURF effect due to the lightly doped n-drift region.…”

Section: Electrical Model For Hv-ldmossmentioning

confidence: 99%

Development of scalable electrical models for high-voltage LDMOS

Sukeshwar

Bruce

Friedrich

et al. 2012

Proceedings of the 7th International Power Electronics and Motion Control Conference

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This paper presents a scalable electrical model for high-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to determine the I-V characteristics, which can be used in SPICE simulators. This scalable model is represented as a hybrid model by computing its transfer function to enable its wide use in testing high-voltage devices. The scalable model has been validated for different device geometries including both large and small gate-channel. The lightly-doped n-drift region is modeled as a parasitic bipolar junction transistor (BJT) and diode which improves the accuracy of the model by exhibiting the quasi-saturation effect when compared to available BSIM models. Furthermore, this model can be incorporated to develop fault models for testing and diagnosis of high-voltage devices. Keywords-High-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS), Bipolar Junction Transistor (BJT), Quasi-saturation Effect, RESURF Effect.I.

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Section: Electrical Model For Hv-ldmossmentioning

confidence: 99%

Development of scalable electrical models for high-voltage LDMOS

Sukeshwar

Bruce

Friedrich

et al. 2012

Proceedings of the 7th International Power Electronics and Motion Control Conference

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“…However, the approximated thermal model is no longer valid for modern power technologies. Robustness of high voltage (HV) or power MOS transistors is often limited not only thermally but also electrically [3]. As a matter of fact, electrical safe operating area (SOA) usually determines the operating boundary of DMOS transistors under very short, high power pulses like ESD when the transistor is used as ESD protection.…”

Section: Introductionmentioning

confidence: 99%

A failure levels study of non-snapback ESD devices for automotive applications

Cao

Glaser

Frei

et al. 2010

2010 IEEE International Reliability Physics Symposium

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Snapback ESD devices suffer from increasing danger when the protected ICs experience ESD events in powered up states. To ensure more reliable ESD protections, non-snapback ESD structures are gaining more importance in the field of automotive ESD design. Two types of on-chip non-snapback ESD devices, pn-diodes and active FET structures are investigated in this work regarding their failure levels. Characteristics of the ESD devices as well as electrical SOA of an nLDMOS are evaluated and discussed in detail with TCAD electro-thermal simulation, SPICE circuit simulation and mainly TLP measurements. Comparison of the efficiency of different ESD protections considering ESD window is also given, delivering the basic idea of choosing the right ESD devices in automotive applications.

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“…Also, it is very challenging to make both n-and p-type VDMOS transistors in the same process flow. Therefore, integrated VDMOS transistors are much less common compared to LDMOS devices [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…Most research is for LDMOS transistors, as these devices are much easier to integrate and as such are more common in smart power technologies. Only a few papers exist on reliability assessment of integrated VDMOS transistors [13][14][15]30].…”

Section: Introductionmentioning

confidence: 99%