On the Feasibility of an Inverter-Based CMOS Envelope Detector

Analysis of an Inverter-Based CMOS Envelope Detector

“…The power consumption of wake-up receivers can be significantly reduced by using an envelope detector which eliminates the need for RF amplification and generation of LO frequency [2]. Figure 1(a) shows the inverter-based CMOS envelope detector first reported in [3]. In contrast to prior envelopedetector designs which utilized distortion in elementary amplifiers such as a common-drain amplifier [4], a common-gate amplifier [5], and a common-source amplifier [6], the inverterbased envelope detector uses the second order distortion current generated by an inverter biased in the subthreshold region to generate conversion gain [3].…”

“…Figure 1(a) shows the inverter-based CMOS envelope detector first reported in [3]. In contrast to prior envelopedetector designs which utilized distortion in elementary amplifiers such as a common-drain amplifier [4], a common-gate amplifier [5], and a common-source amplifier [6], the inverterbased envelope detector uses the second order distortion current generated by an inverter biased in the subthreshold region to generate conversion gain [3]. The conversion gain is maximized with the transistors biased in the subthreshold region.…”

“…The conversion gain is maximized with the transistors biased in the subthreshold region. The conversion gain is sensitive to small variations of the gate bias voltage [3]. [3] showed that by using a chargescaling digital-to-analog conversion (DAC) circuit to generate the gate bias voltage, the circuit's sensitivity to the gate bias voltage is mitigated.…”

“…The conversion gain is sensitive to small variations of the gate bias voltage [3]. [3] showed that by using a chargescaling digital-to-analog conversion (DAC) circuit to generate the gate bias voltage, the circuit's sensitivity to the gate bias voltage is mitigated. [3] shows that it is feasible to generate conversion gain with a digital inverter, but does not describe the underlying theoretical framework for generating the conversion gain.…”

“…[3] showed that by using a chargescaling digital-to-analog conversion (DAC) circuit to generate the gate bias voltage, the circuit's sensitivity to the gate bias voltage is mitigated. [3] shows that it is feasible to generate conversion gain with a digital inverter, but does not describe the underlying theoretical framework for generating the conversion gain. This article addresses the knowledge gap by deriving the voltage transfer characteristic (VTC), the small signal gain, and the scaling factor of the inverter-based envelope detector biased in the subthreshold region.…”