2013 14th International Workshop on Microprocessor Test and Verification 2013
DOI: 10.1109/mtv.2013.10
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On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors

Abstract: When the result of a previous instruction is needed in the pipeline before it is available, a "data hazard" occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic; its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes f… Show more

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Cited by 18 publications
(4 citation statements)
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“…Software-Based Self-Test (SBST) [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] is an emerging paradigm in the test field. The major problem with SBST is usually the not sufficient test quality, measured by the single Stuck-at-Fault (SAF) coverage, let alone considering broader fault classes.…”
Section: Introductionmentioning
confidence: 99%
“…Software-Based Self-Test (SBST) [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] is an emerging paradigm in the test field. The major problem with SBST is usually the not sufficient test quality, measured by the single Stuck-at-Fault (SAF) coverage, let alone considering broader fault classes.…”
Section: Introductionmentioning
confidence: 99%
“…In [21], a method is proposed, which can enhance SBST program in order to bring more coverage to pipeline logic and also memory addressing. Another approach for testing the pipeline was made in [22]. The proposed strategy involves the activation of faults related to the data hazards and register forwarding logic in processor core, and later research concentrates on decode stage of the pipeline [5].…”
Section: Introductionmentioning
confidence: 99%
“…As it is shown in Section 5.2, even the simple task of fault simulating 50Kbytes of test code on the OpenRISC OR1200 processor using commercial tools, requires several days for stuck-at faults and even weeks for transition faults. By taking into account that test-generation is highly complex and even more CPU-intensive than fault simulation, we understand why most SBST methods target only the stuckat fault model [136,190,172,138,169,171,175,176,177,178,179,180,181,182,183,184,185,186,189,191].…”
Section: Motivationmentioning
confidence: 99%
“…Various methods target microprocessors with caches [173], shared-memory schemes [174], floating-point units [175] and dual-issue processors [176]. Deterministic techniques exploit the regularity of sub-modules [177,178,179,180,181,182,183], while others use ATPG [184] and evolutionary algorithms [184,185,186]. Several methods explore the application of SBST to test peripheral modules [187,188].…”
Section: Introductionmentioning
confidence: 99%