On the hardware implementation of digital signal processors

Peled, A.

doi:10.1109/tassp.1976.1162774

Cited by 68 publications

(8 citation statements)

References 12 publications

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“…[Peled 1976;Khoo et al 1996;Skaf and Boyd 2008]. In these works, the constant multipliers are encoded in CSD form, whereas the multiplicands are encoded in normal binary form.…”

Section: Second Improvement: the Proposed Significant Position Encodingmentioning

confidence: 99%

“…We have used C++ and VHDL (behavior) implementations of the forward propagation of CNNs using SPE as a data type for the MNIST handwritten recognition task and GRSTB. The topology of our network for the MNIST handwritten task is a simple CNN based on proposition of Simard et al [2003], which uses two combined convolutionalsubsampling layers (a convolution kernel size of 5 and a subsampling of 2) as feature extraction (cf. Figure 6).…”

Section: Software Implementationmentioning

confidence: 99%

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Efficient Data Encoding for Convolutional Neural Network application

Trinh

Duranton

Paindavoine

2015

ACM Trans. Archit. Code Optim.

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This article presents an approximate data encoding scheme called Significant Position Encoding (SPE). The encoding allows efficient implementation of the recall phase (forward propagation pass) of Convolutional Neural Networks (CNN)-a typical Feed-Forward Neural Network. This implementation uses only 7 bits data representation and achieves almost the same classification performance compared with the initial network: on MNIST handwriting recognition task, using this data encoding scheme losses only 0.03% in terms of recognition rate (99.27% vs. 99.3%). In terms of storage, we achieve a 12.5% gain compared with an 8 bits fixed-point implementation of the same CNN. Moreover, this data encoding allows efficient implementation of processing unit thanks to the simplicity of scalar product operation-the principal operation in a FeedForward Neural Network.

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“…[Peled 1976;Khoo et al 1996;Skaf and Boyd 2008]. In these works, the constant multipliers are encoded in CSD form, whereas the multiplicands are encoded in normal binary form.…”

Section: Second Improvement: the Proposed Significant Position Encodingmentioning

confidence: 99%

Section: Software Implementationmentioning

confidence: 99%

Efficient Data Encoding for Convolutional Neural Network application

Trinh

Duranton

Paindavoine

2015

ACM Trans. Archit. Code Optim.

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“…The architecture for the RSP was developed from a few key concepts concerning common functions involved in signal processing [1], Concurrent with the development of these ideas was Winograd's work on reducing the arithmetic complexity of the Discrete Fourier Transform (DFT) [2], and the work of Agarwal and Cooky on digital convolutions [3]. The architecture and organization of this processor and its subsequent evolution are described in the paper by Mintzer and Peled in this issue [4].…”

Section: Introductionmentioning

confidence: 99%

Real-Time Signal Processor Software Support

Davies

Ris

1982

IBM J. Res. & Dev.

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The Real-Time Signal Processor (RSP) is a microprocessor optimized to provide fast, cost-efficient processing for signal processing applications. In order for the RSP to become fully useful, a complete set of software support tools needed to be developed. The hardware design and software development, which took place between 1978 and 1980, resulted in many architectural features which minimized hardware complexity at the expense of programmability. This paper describes the tools that were developed and the decisions that were involved, and includes hindsight comments on what was done. Particular emphasis is placed on the most interesting aspects of the software development, i.e., how the special architectural features of the RSP were handled to make the overall hardware/software .tystem more programmable.

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“…The major application objective of the microcomputer system has been that the system should be cable of implementing selfadaptive configurations, based on defined filter design criteria [16][17][18][19][20][21][22]. The specification of the unit to achieve this function was interpreted as follows:…”

Section: Introductionmentioning

confidence: 99%

Design of a bit-slice microcomputer

Neale¹,

Clark²,

Wilson³

1981

IEE Proc. E Comput. Digit. Tech. UK

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The fact that the synthesis of a microcomputer, to achieve the specific requirements for real-time operation, can be achieved through bit-slice technology is utilised as a design factor. The paper presents the design of a 3 MHz clock frequency microprogrammable microcomputer based on the Intel 3000 series of microprocessors. The requirements of real-time signal processing are included in the computer specification, as are facilities to incorporate incircuit emulation for software development. The paper discusses the microprogramming technique and illustrates the flexibility of the microcode through the jump-function facility. The paper evaluates the performance to achieve a worst-case cycle time of 383 ns without pipelining and carry look ahead as opposed to a worse case of 149 ns with pipelining and carry look ahead. A 3 MHz clock frequency was easily achieved without pipelining.

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On the hardware implementation of digital signal processors

Cited by 68 publications

References 12 publications

Efficient Data Encoding for Convolutional Neural Network application

Efficient Data Encoding for Convolutional Neural Network application

Real-Time Signal Processor Software Support

Design of a bit-slice microcomputer

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