On the implementation of a three-operand multiplier

This paper presents a three-integers multiplication algorithm R = A * X * Y for Reconfigurable Mesh (RM). It is based on a three-integer multiplication algorithm for faster FPGA implementations. We show that multiplying three integers of n bits can be performed on a 3D RM of size (3n +log n + 1)× (2 √ n + 1+3)× √ n + 1 using 44 + 18 · log log MNO steps, where MNO is a bound which is related to the number of sequences of '1's in the multiplied numbers. The value of MNO is bounded by n but experimentally we show that on the average it is √ n. Two algorithms for solving multiplication on a RM exists and their techniques are asymptotically better time wise, O(1) and O(log * n), but they suffer from large hidden constants and slow data insertion time ( O( √ n)) respectively. The proposed algorithm is relatively simple and faster on the average (via sampling input values) then the previous two algorithms thus contributes in making the RM a practical and feasible model. Our experiments show a significant improvement in the expected number of elementary operations for the proposed algorithm.

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“…[6] addressed the problem of implementing threeoperand multiplier. They compared three methods for multiplying three operand.…”

Section: Related Workmentioning

confidence: 99%

Adaptive Booth Algorithm for Three-Integers Multiplication for Reconfigurable Mesh

Stein

Asher

2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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“…In [14], a fresh method for a three-operand multiplier is given, featuring a basic two-level radix-4 recoding technique to minimize costs and latency compared to other techniques. An elliptic curve cryptographic processor that supports 256-bit point multiplication is proposed in [15].…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations

Usha,

Kanthimathi

2024

ICST Transactions on Scalable Information Systems

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Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay. Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operation. The canonical types of PPA result in a lesser path delay of approximately O (log2 n). These adders can be designed for 8, 16, 24 or n bits. But this work is focused on developing a 24-bit three-operand adder that takes three 24-bit binary numbers as input and generates a 24-bit sum output and a carry using five different PPA methods The proposed summing circuits are operationalized with Hardware-Description-Language (HDL) using Verilog, and then subjected to synthesis using Field -Programmable Gate- Array (FPGA) Vertex 5. On comparing the proposed adders, it shows that the delay and the size occupied are significantly less in the Sklansky PPA. These faster three-operand adders can be utilized for three-operand multiplication in image processing applications and Internet of Things (IoT) security systems.

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“…Regarding the design and implementation of multipliers, there exist several studies using multi-operand multipliers [19,20,21].…”

Section: Classical Multiplication Of Three-operand Multipliermentioning

confidence: 99%

“…By applying the multi-operand adders and parallel multiplication scheme and their combination, the author in [19] was able to design and introduce a fast multi-operand multiplier. A three-operand multiplier is presented in [20], which, three methods are introduced for implementation. In the first method, two multipliers are set in series.…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

Reshadinezhad

Charmchi²,

Navi³

2015

IJMECS

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Abstract-Multiplication scheme is one of the most essential factors, which is time consuming. Designers and manufacturers of processors emphasis on methods which would not only perform the multiplication scheme in a rapid manner, but would reduce the physical aspect of the design as well; hence, a reduction in power consumption. Addition is one of the fundamental factors in multiplication. Pre-designing of circuits and transistors' levels used to be made through Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but now, due to scaling and difficulties thereof, new technologies like Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA) and Carbon Nanotube Field Effect Transistor (CNFET) are introduced. Among the new technologies, CNFET has become center of attention due to similarities in electronic features in relation to MOSFET. A comparison made between CNFET with MOSFET technologies indicate that, power delay product (PDP) and power leakage can be less in nanotube transistors. Field effect transistor circuit's simulations are accomplished through HSPICE simulator. The simulation results indicate that this proposed Three-operand Carbon Nanotube Multiplier has a better performance in comparison with the threeoperand multiplication done on computers nowadays, which we call it classical multiplier in this article.

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On the implementation of a three-operand multiplier

Cited by 4 publications

References 7 publications

Adaptive Booth Algorithm for Three-Integers Multiplication for Reconfigurable Mesh

Adaptive Booth Algorithm for Three-Integers Multiplication for Reconfigurable Mesh

Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations

Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

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