On the limits of gate elimination

Golovnev, Alexander; Hirsch, Edward; Knop, Alexander

doi:10.1016/j.jcss.2018.04.005

Cited by 4 publications

(3 citation statements)

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“…It should be noted that known satisfiability algorithms based on branching, as well as circuit lower bounds based on gate elimination [PPZ97, PPSZ05, Sch05, San10, CK15] may be viewed as depth-reductions for small circuits: if at most k variables are set in any branch before the circuit has a "trivial" form, then the circuit can be expressed as an OR of 2 k "trivial" forms. At the same time, the known techniques in this line of work appear stuck at lower bounds of around 3n, and provably cannot go beyond linear-size bounds [GHKK18].…”

Section: Our Resultsmentioning

confidence: 99%

“…If no depth-3 circuit of this form exists for some linear-size circuits, then we would have a separation between linear-size circuits and (for example) super-linear-size series-parallel circuits (by Valiant's reduction for such circuits, see Theorem 2.1). Note that for the gate elimination method such limitations are known [GHKK18], and they do not apply to the approach presented in this work.…”

Section: Our Resultsmentioning

confidence: 99%

“…It is difficult to imagine a proof of 5n lower bound using these ideas. This intuition was recently made formal in [GHKK18], where it was shown that a certain formalization of the gate elimination technique is unable to obtain a stronger than 5n lower bound. Therefore we must find new approaches for proving lower bounds against circuits of unbounded depth.…”

Section: Introductionmentioning

confidence: 99%

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Circuit Depth Reductions

Golovnev¹,

Williams²

2018

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The best known size lower bounds against unrestricted circuits have remained around 3n for several decades. Moreover, the only known technique for proving lower bounds in this model, gate elimination, is inherently limited to proving lower bounds of less than 5n. In this work, we propose a non-gate-elimination approach for obtaining circuit lower bounds, via certain depththree lower bounds. We prove that every (unbounded-depth) circuit of size s can be expressed as an OR of 2 s/3.9 16-CNFs. For DeMorgan formulas, the best known size lower bounds have been stuck at around n 3−o(1) for decades. Under a plausible hypothesis about probabilistic polynomials, we show that n 4−ε -size DeMorgan formulas have 2 n 1−Ω(ε) -size depth-3 circuits which are approximate sums of n 1−Ω(ε) -degree polynomials over F 2 . While these structural results do not immediately lead to new lower bounds, they do suggest new avenues of attack on these longstanding lower bound problems.Our results complement the classical depth-3 reduction results of Valiant, which show that logarithmic-depth circuits of linear size can be computed by an OR of 2 εn n δ -CNFs, and slightly stronger results for series-parallel circuits. It is known that no purely graph-theoretic reduction could yield interesting depth-3 circuits from circuits of super-logarithmic depth. We overcome this limitation (for small-size circuits) by taking into account both the graph-theoretic and functional properties of circuits and formulas.We show that improvements of the following pseudorandom constructions imply super-linear circuit lower bounds for log-depth circuits via Valiant's reduction: dispersers for varieties, correlation with constant degree polynomials, matrix rigidity, and hardness for depth-3 circuits with constant bottom fan-in. On the other hand, our depth reductions show that even modest improvements of the known constructions give elementary proofs of improved (but still linear) circuit lower bounds.

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Section: Our Resultsmentioning

confidence: 99%

Section: Our Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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