On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

Simoen, Eddy; Verheyen, Peter; Shickova, A.; Loo, Roger; Claeys, Cor

doi:10.1109/led.2007.906437

Cited by 22 publications

(10 citation statements)

References 14 publications

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“…For pMOSFETs, the introduction of the SiGe material into source/drain (S/D) regions can provide an uniaxial compressive strain in the channel. This brings about a significant enhancement of pMOSFETs performance [16]. However, the use of HK/metal gate (MG) gatestacks and SiGe S/D scheme usually accompanies processinduced defects at insulator/semiconductor interface and/or internal insulator.…”

Section: Impact Of Uniaxial Strain On Random Telegraphmentioning

confidence: 99%

Impact of Uniaxial Strain on Random Telegraph Noise in High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula>/Metal Gate pMOSFETs

Huang¹,

Chen²,

Tsai³

et al. 2015

IEEE Trans. Electron Devices

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The random telegraph noise (RTN) characteristics of high-k (HK)/metal gate (MG) pMOSFETs with uniaxial compressive strain have been investigated. The configurationcoordinate diagram and band diagram are both established by extracting trap parameters, including capture and emission time, activation energy for capture and emission, trap energy level, and trap location in gate dielectric. Through a comparison of RTN results and gate-leakage current density ( J G ) between HK/MG pMOSFETs with and without uniaxial compressive strain in channel, it is found that the trap position from the insulator/semiconductor interface is reduced in the uniaxial compressive strained HK/MG pMOSFETs. This is reasonably attributed to the strain-increased tunneling barrier height and out-of-plane effective mass, which brings about the reduction in the tunneling attenuation length. Meanwhile, it can also be demonstrated by the lower J G in uniaxial compressive strained HK/MG pMOSFETs. Index Terms-High-k (HK)/metal gate (MG) pMOSFETs, random telegraph noise (RTN), SiGe source/drain (S/D), uniaxial compressive strain.

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Section: Impact Of Uniaxial Strain On Random Telegraphmentioning

confidence: 99%

Impact of Uniaxial Strain on Random Telegraph Noise in High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula>/Metal Gate pMOSFETs

Huang¹,

Chen²,

Tsai³

et al. 2015

IEEE Trans. Electron Devices

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“…For HfSiON/SiO 2 and a fully silicided gate stack, the 1/f noise is not affected by SiGe stressors, indicating that the embedded (source/ drain) processing does not degrade the quality of the gate stack and that the intrinsic strain does not affect 1/f noise. 71 Briefly, strain engineering, when properly characterized and implemented, has only a marginal impact on oxide quality and does not compromise long-term reliability. Strain has no intrinsic effect on 1/f noise.…”

Section: Reliability Issuesmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

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“…The introduction of channel strain engineering in the state-of-the-art CMOS technology is recognized as an indispensable performance booster in producing next generation CMOS devices [8,9]. For p-type MOSFET (pMOSFET), using embedded SiGe in the recessed source/drain (S/D) region can efficiently provide uniaxial compressive strain in the channel and improve hole mobility, bringing the enhancement of device performance [10][11][12]. In addition, high-k (HK) materials are also adopted into advanced CMOS process for solving the increased gate leakage current.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Low‐Frequency Noise Characterization of 28‐nm High‐k pMOSFET with Embedded SiGe Source/Drain

Tsai

Chen

et al. 2014

Journal of Nanomaterials

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We have studied the low-frequency noise characterizations in 28-nm high-k (HK) pMOSFET with embedded SiGe source/drain (S/D) through 1/ noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFET with embedded SiGe S/D. The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO 2 interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower 1/ noise level in HK pMOSFET with embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low-frequency noise characteristics.

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On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

Cited by 22 publications

References 14 publications

Impact of Uniaxial Strain on Random Telegraph Noise in High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula>/Metal Gate pMOSFETs

Impact of Uniaxial Strain on Random Telegraph Noise in High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula>/Metal Gate pMOSFETs

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Investigation of Low‐Frequency Noise Characterization of 28‐nm High‐k pMOSFET with Embedded SiGe Source/Drain

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