On the memory system requirements of future scientific applications: Four case-studies

Pavlovic, Milan; Etsion, Yoav; Ramírez, Alex

doi:10.1109/iiswc.2011.6114176

Cited by 21 publications

(19 citation statements)

References 12 publications

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“…The hubs, introduced in Section III, are switches interfacing the intra-cluster networks with the intercluster one. E-link-intra 0.25/0.50 pJ/bit (2.5/5 mm) E-link-inter 15.5 pJ/bit (12.5 cm) E-switch-dyn (4 port) 1 81.79 pJ/flit (x16) P-switch-static (4 port) 47.96 mW (x16) E-switch-dyn (6 port) 2 125.69 pJ/flit (x64) P-switch-static (6 port) 73.05 mW (x64) E-hub-dyn (7 port) 3 91.39 pJ/flit (x4) P-hub-static (7 port) 51.39 mW 4 (x4)…”

Section: A Simulation and Evaluation Methodologymentioning

confidence: 99%

“…These systems are very demanding from the memory bandwidth point of view because of the aggregate requirements of the constantly increasing number of cores per chip [3], [4]. On top of that, latency for accessing the memory hierarchy is typically the key to application performance and in some cases even more important than available bandwidth [5].…”

Section: Introductionmentioning

confidence: 99%

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Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Grani

Hendry

Bartolini

et al. 2015

2015 International Conference on Computing, Networking and Communications (ICNC)

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Speed-up in computing systems today is most often accomplished by increasing parallelism in both hardware and software. Parallel applications residing wholly on a single multicore chip generally utilize implicit inter-thread communication via shared memory managed by cache-coherency mechanisms. However, increasing parallelism by creating coherent domains across many chips poses new challenges. In this work, we illustrate the sensitivity of various applications on a theoretical four-socket system to the latency of their coherency traffic, and show that current solutions, such as Quick Path Interconnect (QPI) and HyperTransport (HT), could benefit greatly from a lower latency communication medium. Then, we propose a silicon photonic inter-chip network that achieves very low-latency and falls within a reasonable power budget.

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Section: A Simulation and Evaluation Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Grani

Hendry

Bartolini

et al. 2015

2015 International Conference on Computing, Networking and Communications (ICNC)

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“…Dynamic energy is the product of the energy for a load or store and the number of loads and stores for each level of the memory hierarchy for a level, as shown in equation (3). Static energy is estimated as product of time (T) and static power of the memory hierarchy illustrated in equation (4). The static power is calculated as sum of static power of each level of cache and the refresh power of DRAM/eDRAM in the memory hierarchy.…”

Section: )mentioning

confidence: 99%

“…the memory wall [1]) and this gap in the performance of CPU and memory sub-systems will only increase further for future many-core systems [2]. Second, there is a growing capacity gap due to the limited scaling of DRAM, power, and cost limitations [3,4]. Finally, at the current DDR3 powerperformance level of approximately 600 MW/GB/s, in an Exascale system, the memory alone would draw 600MW [2].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of emerging memory technologies for HPC, data intensive applications

Suresh

Cicotti

Carrington

2014

2014 IEEE International Conference on Cluster Computing (CLUSTER)

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DRAM technology has several shortcomings in terms of performance, energy efficiency and scaling. Several emerging memory technologies have the potential to compensate for the limitations of DRAM when replacing or complementing DRAM in the memory sub-system. In this paper, we evaluate the impact of emerging technologies on HPC and data-intensive workloads modeling a 5-level hybrid memory hierarchy design. Our results show that 1) an additional level of faster DRAM technology (i.e. EDRAM or HMC) interposed between the last level cache and DRAM can improve performance and energy efficiency, 2) a non-volatile main memory (i.e. PCM, STTRAM, or FeRAM) with a small DRAM acting as a cache can reduce the cost and energy consumption at large capacities, and 3) a combination of the two approaches, which essentially replaces the traditional DRAM with a small EDRAM or HMC cache between the last level cache and the non-volatile memory, can grant capacity and improved performance and energy efficiency. We also explore a hybrid DRAM-NVM design with a partitioned address space and find that this approach is marginally beneficial compared to the simpler 5-level design. Finally, we generalize our analysis and show the impact of emerging technologies for a range of latency and energy parameters.

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“…A recent study has shown that the increase of the number of cores on a single chip puts great stress on the off-chip memory memory system: when executed on a 128-core system, HPC applications require 64 GB of capacity and may require up to 64 GB/s of off-chip memory bandwidth [10]. It is clear that current memory systems will not be able to sustain these requirements when the number of cores begins to increase.…”

Section: Introductionmentioning

confidence: 99%

Data placement in HPC architectures with heterogeneous off-chip memory

Pavlovic

Puzovic

Ramírez

2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The limitations of traditional memory technologies are pushing research in the direction of hybrid memory systems that, besides DRAM, include one or more modules based on some of the higherdensity non-volatile memory technologies, where one of them will provide the required bandwidth, while the other will provide the required capacity for the application. This creates many challenges with data placement and migration policies between the modules of such hybrid memory system. In this paper, we propose an architecture with a hybrid memory design that places two technologically different memory modules in a flat address space. On such system, we evaluate several HPC workloads against different data placement and migration policies, compare their performance by means of execution time and the number of non-volatile memory writes, and consider how it can be applied to the future HPC architectures. Our results show that the hybrid memory system with dynamic page migration and limited DRAM capacity, can achieve performance that is comparable to a hypothetical, hard to implement, DRAM-only system.

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On the memory system requirements of future scientific applications: Four case-studies

Cited by 21 publications

References 12 publications

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Evaluation of emerging memory technologies for HPC, data intensive applications

Data placement in HPC architectures with heterogeneous off-chip memory

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