On the origins of near-surface stresses in silicon around Cu-filled and CNT-filled through silicon vias

Abstract

Micro-Raman spectroscopy was employed to study the near-surface stress distributions and origins in Si around through silicon vias (TSVs) at both room temperature and elevated temperatures for Cu-filled and CNT-filled TSV samples. From the observations, we proved that the stresses near TSVs are mainly from two sources: 1) pre-existing stress before via filling, and 2) coefficients of thermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress is shown to dominate the compressive regime of the near-surface stress distribution around Cu-filled TSV structures, while pre-existing stress dominates the full range of the stress distribution in the CNT-filled TSV structures. Once the pre-existing stress is minimized, the total stress around CNT-filled TSVs can be minimized accordingly. Therefore, compared to Cu-filled TSVs, CNT-filled TSVs hold the potential to circumvent the hassle of stress-aware circuit layout and to solve the stress-related reliability issues.

A photo‐elastic microscopy study of the temperature dependency of stress induced by through silicon vias in silicon

“…This resulted in a zero-stress temperature of 340 K by means of extrapolation. The value of T 0 seems to be relatively low in view of usual process temperatures >>400 K (e.g., [6,9,10]) but it is close to that one determined in the copper of TSV by Liu et al [11].…”

“…Even if the TSV technology has been established as a standard process it lacks non-destructive and fast characterization tools for process optimization and quality control. As a complement to the versatile simulation studies (e.g., [5,6]) Scanning Acoustic Microscopy and Photo-elastic Microscopy have been under discussion [7] as an alternative to Raman microscopy (e.g., [8][9][10][11]) and X-ray diffraction [12].…”

Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

“…It could be due to the difference of CTE between SiO2 and Si for the same reason as above. A last source is discussed in [12] where the authors gave clear evidence that residual Si stress existing around a metalized TSV is not only due to CTE mismatch between Cu and Si but also from a pre-existing stress present before the TSV Cu filling. They suspect this preexisting stress to be originating from the thermal growth technique of the oxide insulator.…”

Shallow trench isolation structure design for through‐silicon vias stress reduction

“…It is found that compared to the TSV filled with copper isolation layer filled with BCB, the TSV filled with the solder core and the p‐toluene‐HT isolation layer, the thermal stress will be smaller 10–14 . Ye Zhu et al proposed that carbon nanotubes can be used instead of copper as the filling material of TSV, because carbon nanotubes have higher thermal conductivity 15 . Although the replacement of copper with organic materials greatly reduces the thermal stress caused by CTE mismatch, the abovementioned methods are not compatible with the CMOS process and will increase the process cost.…”

“…[10][11][12][13][14] Ye Zhu et al proposed that carbon nanotubes can be used instead of copper as the filling material of TSV, because carbon nanotubes have higher thermal conductivity. 15 Although the replacement of copper with organic materials greatly reduces the thermal stress caused by CTE mismatch, the abovementioned methods are not compatible with the CMOS process and will increase the process cost.…”