On the removal of anti and output dependences

Calland, Pierre-Yves; Darte, Alain; Robert, Yves; Vivien, Frédéric

doi:10.1109/asap.1996.542829

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…Post-register allocation scheduling has the advantage of including spill code in the schedule, but suffers from increased flow, anti-and output dependences [23]. Pre-register allocation scheduling increases live-ranges, and hence interference, causing extra spills that do not get scheduled.…”

Section: Instruction Scheduling and Register Allocationmentioning

confidence: 99%

A framework for reducing instruction scheduling overhead in dynamic compilers

Tang

Siu

Vasilevskiy

et al. 2006

Proceedings of the 2006 Conference of the Center for Advanced Studies on Collaborative Research - CASCON '06

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Start-up time is a serious concern for highavailability applications such as web servers, transaction managers, and batch processes. Compilation time contributes directly to start-up costs in dynamic compilers. Up to 30% of compilation time is spent scheduling instructions in the IBM® Testarossa just-in-time compiler. In this paper, we describe a scheduling framework that reduces scheduling overhead by up to 61% with little to no degradation in throughput performance.By combining online profiledirected feedback data with information generated during register allocation, our framework identifies code regions that will benefit most from instruction scheduling.We evaluate our framework on typical client-side applications, multi-threaded server applications to production application servers on the IBM® zSeries® 990 and POWER4™ platforms. 1

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Section: Instruction Scheduling and Register Allocationmentioning

confidence: 99%

A framework for reducing instruction scheduling overhead in dynamic compilers

Tang

Siu

Vasilevskiy

et al. 2006

Proceedings of the 2006 Conference of the Center for Advanced Studies on Collaborative Research - CASCON '06

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“…This is usually done by array expansion or introducing new temporary arrays and associated copy operations [7], [11], [35], [43].…”

Section: Dependence Eliminationmentioning

confidence: 99%

Automatic Parallelization of Tiled Loop Nests with Enhanced Fine-Grained Parallelism on GPUs

Peng

et al. 2012

2012 41st International Conference on Parallel Processing

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Abstract-Automatically parallelizing loop nests into CUDA kernels must exploit the full potential of GPUs to obtain high performance. One state-of-the-art approach makes use of the polyhedral model to extract parallelism from a loop nest by applying a sequence of affine transformations to the loop nest. However, how to automate this process to exploit both intraand inter-SM parallelism for GPUs remains a challenging problem. Presently, compilers may generate code significantly slower than hand-optimized code for certain applications.This paper describes a compiler framework for tiling and parallelizing loop nests with uniform dependences into CUDA code. We aim to improve two levels of wavefront parallelism. We find tiling hyperplanes by embedding parallelismenhancing constraints in the polyhedral model to maximize intra-tile, i.e., intra-SM parallelism. This improves the load balance among the SPs in an SM executing a wavefront of loop iterations within a tile. We eliminate parallelism-hindering false dependences to maximize inter-tile, i.e., inter-SM parallelism. This improves the load balance among the SMs executing a wavefront of tiles. Our approach has been implemented in PLUTO and validated using eight benchmarks on two different NVIDIA GPUs (C1060 and C2050). Compared to PLUTO, our approach achieves 2 -5.5X speedups across the benchmarks. Compared to highly hand-optimized 1-D Jacobi (3 points), 2-D Jacobi (5 points), 3-D Jacobi (7 points) and 3-D Jacobi (27 points), our speedups, 1.17X, 1.41X, 0.97X and 0.87X with an average of 1.10X on C1060 and 1.24X, 1.20X, 0.86X and 0.95X with an average of 1.06X on C2050, are competitive.

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Generating efficient tiled code for distributed memory machines

Tang¹,

Xue²

2000

Parallel Computing

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On the removal of anti and output dependences

Cited by 5 publications

References 8 publications

A framework for reducing instruction scheduling overhead in dynamic compilers

A framework for reducing instruction scheduling overhead in dynamic compilers

Automatic Parallelization of Tiled Loop Nests with Enhanced Fine-Grained Parallelism on GPUs

Generating efficient tiled code for distributed memory machines

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