On the reuse of timing resilient architecture for testing path delay faults in critical paths

Kuentzer, Felipe A.; Juracy, Leonardo R.; Amory, Alexandre M.

doi:10.23919/date.2018.8342039

Cited by 5 publications

(2 citation statements)

References 24 publications

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“…Finally, Kuentzer et al explore the testing characteristics of the resilient bundled-data template called Blade [29], [30]. First, the authors analyze and classify the faults in the error detection logic (EDL) of the Blade template [29], proposing slight modification in the EDL design to increase controllability/observability.…”

Section: Related Workmentioning

confidence: 99%

“…First, the authors analyze and classify the faults in the error detection logic (EDL) of the Blade template [29], proposing slight modification in the EDL design to increase controllability/observability. As the resilient architecture of the Blade template is capable to detect timing violations during operation, it also implies that the architecture also enables online delay testing of critical paths [30].…”

Section: Related Workmentioning

confidence: 99%

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At-speed DfT Architecture for Bundled-data Design

Guazzelli

Fesquet

2020

2020 IEEE International Test Conference (ITC)

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At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature -by adapting the existing techniques for synchronous or creating new ones from scratch -those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%