On the Self-Repair Role of Astrocytes in STDP Enabled Unsupervised SNNs

Rastogi, Mehul; Lu, Sen; Islam, Nafiul; Sengupta, Abhronil

doi:10.3389/fnins.2020.603796

Cited by 16 publications

(14 citation statements)

References 41 publications

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“…Rastogi et al [27] recently demonstrated SNAN designs using the MNIST dataset, where astrocytes modulate the presynaptic neuron release probability during faults when synaptic learning is stuck at zero. In this case, the astrocytes indirectly modulate synaptic activities.…”

Section: Discussionmentioning

confidence: 99%

“…This study is a proof of concept that astrocytes can be employed in image recognition to improve SNNs performance. While recent examples include the bio-inspired neuron-astrocyte network for image classification [25, 26] and the unsupervised network with self-repair in the event of synaptic failure [27], astrocytes employed here are for neural support rather than as computational units.…”

Section: Introductionmentioning

confidence: 99%

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Spiking Neuron-Astrocyte Networks for Image Recognition

Lorenzo,

Rico-Gallego,

Binczak

et al. 2024

Preprint

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From biological and artificial network perspectives, researchers have started acknowledging astrocytes as computational units mediating neural processes. Here, we propose a novel biologically-inspired neuron-astrocyte network model for image recognition, one of the first attempts at implementing astrocytes in Spiking Neuron Networks (SNNs) using a standard dataset. The architecture for image recognition has three primary units: the pre-processing unit for converting the image pixels into spiking patterns, the neuron-astrocyte network forming bipartite (neural onnections) and tripartite synapses (neural and astrocytic connections), and the classifier unit. In the astrocyte-mediated SNNs, an astrocyte integrates neural signals following the simplified Postnov model. It then modulates the Integrateand-Fire (IF) neurons via gliotransmission, thereby strengthening the synaptic connections of the neurons within the astrocytic territory. We develop an architecture derived from a baseline SNN model for unsupervised digit classification. The Spiking Neuron-Astrocyte Networks (SNANs) display better network performance with an optimal variance-bias trade-off than SNN alone. We demonstrate that astrocytes promote faster learning, support memory formation and recognition, and provide a simplified network architecture. Our proposed SNAN can serve as a benchmark for future researchers on astrocyte implementation in artificial networks, particularly in neuromorphic systems, for its simplified design.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Spiking Neuron-Astrocyte Networks for Image Recognition

Lorenzo,

Rico-Gallego,

Binczak

et al. 2024

Preprint

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“…In neural networks, STDP is an unsupervised learning rule where synaptic weight is modified based on the time window, ∆T, between pre-synaptic and post-synaptic impulses [19]. The change in the synaptic weight is modeled by Equation 8, where A + and A − are constant values representing the potentiation and depression of neurons, τ + and τ − are constants influencing the slope of the function, the time window ∆t is considered between pre-synaptic and post-synaptic impulses [20].…”

Section: Spike-timing-dependent Plasticitymentioning

confidence: 99%

Analog Implementation of a Spiking Neuron with Memristive Synapses for Deep Learning Processing

Ramirez-Morales,

Ponce-Ponce,

Molina-Lozano

et al. 2024

Preprint

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Analog neuromorphic prototyping is crucial for creating spiking neuron models that use memristive devices as synapses to design integrated circuits that leverage on-chip parallel deep neural networks. These models mimic how biological neurons in the brain communicate through electrical potentials. Doing so enables more powerful and efficient functionality than traditional artificial neural networks that run on von Neumann computers or graphic processing unit-based platforms. This technology can accelerate deep learning processing, aiming to exploit the brain’s unique features of asynchronous and event-driven processing by leveraging neuromorphic hardware’s inherent parallelism and analog computation capabilities. Therefore, this paper presents the design and implementation of a leaky integrate and fire neuron prototype implemented with commercially available components on a PCB board. Simulations conducted in LTSpice agree well with the electrical test measurements. The results demonstrate that this design can be employed to interconnect many boards to build layers of physical spiking neurons, interconnected with spike-timing-dependent plasticity as the primary learning algorithm, contributing to the realization of experiments in the early stage of adopting neuromorphic computing.

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“…SNN fault tolerance: Previous works studied the impact of faults on SNN weights without considering the underlying hardware architectures and processing dataflows (Schuman et al, 2020 ; Rastogi et al, 2021 ) and each discussing a specific fault, like bit-flip or synapse removal. Recent works devised mitigation techniques for faults in the weight memories of an SNN hardware (Putra et al, 2021a , b , 2022a ), while work of Putra et al ( 2022b ) aimed at addressing transient faults.…”

Section: Introductionmentioning

confidence: 99%

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

2023

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To maximize the performance and energy efficiency of Spiking Neural Network (SNN) processing on resource-constrained embedded systems, specialized hardware accelerators/chips are employed. However, these SNN chips may suffer from permanent faults which can affect the functionality of weight memory and neuron behavior, thereby causing potentially significant accuracy degradation and system malfunctioning. Such permanent faults may come from manufacturing defects during the fabrication process, and/or from device/transistor damages (e.g., due to wear out) during the run-time operation. However, the impact of permanent faults in SNN chips and the respective mitigation techniques have not been thoroughly investigated yet. Toward this, we propose RescueSNN, a novel methodology to mitigate permanent faults in the compute engine of SNN chips without requiring additional retraining, thereby significantly cutting down the design time and retraining costs, while maintaining the throughput and quality. The key ideas of our RescueSNN methodology are (1) analyzing the characteristics of SNN under permanent faults; (2) leveraging this analysis to improve the SNN fault-tolerance through effective fault-aware mapping (FAM); and (3) devising lightweight hardware enhancements to support FAM. Our FAM technique leverages the fault map of SNN compute engine for (i) minimizing weight corruption when mapping weight bits on the faulty memory cells, and (ii) selectively employing faulty neurons that do not cause significant accuracy degradation to maintain accuracy and throughput, while considering the SNN operations and processing dataflow. The experimental results show that our RescueSNN improves accuracy by up to 80% while maintaining the throughput reduction below 25% in high fault rate (e.g., 0.5 of the potential fault locations), as compared to running SNNs on the faulty chip without mitigation. In this manner, the embedded systems that employ RescueSNN-enhanced chips can efficiently ensure reliable executions against permanent faults during their operational lifetime.

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On the Self-Repair Role of Astrocytes in STDP Enabled Unsupervised SNNs

Cited by 16 publications

References 41 publications

Spiking Neuron-Astrocyte Networks for Image Recognition

Spiking Neuron-Astrocyte Networks for Image Recognition

Analog Implementation of a Spiking Neuron with Memristive Synapses for Deep Learning Processing

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

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