On the Short Circuit Electro-Thermal Failure of 1.2 kV 4H-SiC MOSFETs with 3D Cell Layouts

Abstract

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.

Design and characterization of cell topology effect on SiC VDMOSFETs for high power and frequency applications

“…These techniques include self-aligned channel [2,3], self-aligned source contact [4], specific doping on JFET region [5], and current spreading layer [6]. On the design front, cell topology and pitch reduction play vital roles in further improving the performance of VDMOSFETs [7][8][9][10][11][12][13][14][15][16].…”