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This work presents a comprehensive study on the behaviour and operation of a vertical 1.2 kV 4H-SiC junctionless power FinFET. The increased bulk conduction in the channel of this topology may bring reductions in the channel resistance compared to trench MOSFETs, whose performance is limited by the high interface state density. For this purpose, finite element (FE) simulations are used to examine the operation of this device. It is hence demonstrated that the junctionless FinFET can attain a high average channel drift mobility well above 100 cm2/(Vs), leaving the resistance to be determined by the drift and substrate regions. This allows the FinFET to turn on and reach its steady state current using a much (> 3x) smaller gate overdrive than standard designs. On the other hand, however, the overly high field in the gate oxide, the lack of an efficient mechanism for hole extraction, and the low threshold voltage can cause significant reliability issues. Furthermore, it is shown that the high input capacitance of the FinFET can limit its switching speed to slower levels than in standard trench MOSFETs, which raises the need for further development of the original design proposed for vertical GaN devices. In this context, it is demonstrated that the addition of a p-shield below the trenches can alleviate the off-state reliability issues and increase the speed, while still maintaining a competitive R on  ∼ 2mΩ cm2 even without the use of n-JFET enhancement doping.

In this work, a new model for the mobility due to Coulombic scattering by interface charges (μC) in 4H-SiC MOS structures, which is suitable for device study via finite element (FE)-based simulations, is proposed. Unlike popular expressions based on the classical Sah–Lombardi model which lead to major inconsistencies in μC’s variation with the semiconductor depth z, the proposed model combines previous experimental data with established theoretical results on μC’s depth dependence. The evolution of the components of the channel drift mobility (μch) with z and the gate bias Vgs is then examined using this model by means of FE analysis. It is found that while μC is the dominant component at the surface, at larger depths μch is determined by the mobility due to acoustic phonon scattering (μSA). Moreover, at low channel dopings (NA) or temperatures above approximately 425K,μSA replaces μC as the key limitation. Conversely, the roughness scattering mobility μSR becomes important only at very high Vgs and NA.

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.