On the Signal Filtering Property of CT Incremental Sigma–Delta ADCs

Abstract

In this paper the calculation of the signal behavior and the achievable signal-to-quantization-noise ratio of continuous-time (CT) incremental Sigma-Delta (I-SD) ADCs is described. The presented method allows for the analysis of I-SD ADCs in frequency domain including the specific non-idealities of the CT modulator. In the state of the art, it is described that the omission of the preceding sample-and-hold for the I-SD ADC alters the transfer characteristic compared to a Nyquistrate converter. So far, for CT I-SD ADCs this behavior is only investigated via simulations. In this work the model of a discretetime I-SD ADC is generalized and adapted for the CT case. This allows to analytically obtain the signal and noise transfer function of the I-SD ADC in frequency domain in combination with arbitrary reconstruction filters due to the utilization of the lifting method in a fast and accurate way.

Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF

“…Thus, non-ideal behavior, as finite DC gain and finite gain-bandwidth product (GBW) in continuous-time (CT) I-SD ADCs can not be addressed in a straightforward way. In [7], a general way to calculate the overall NTF is described for CT and DT I-SD ADCs. For the CT case, the calculation approach makes use of the lifting method and is able to directly include non-idealities such as excess-loop-delay (ELD), finite DC gain and finite GBW into calculations [8].…”

“…Whereas the general approach to determine the overall NTF was derived in [7], there was no in-depth analysis on its behavior. Therefore, this work focuses on the properties of the overall NTF of I-SD ADCs, which has, to the authors knowledge, not been covered in literature so far.…”

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

“…In this work, RC topology is chosen for its excellent linearity. In order to suppress the distortion, a high gain loop filter is required [28]. Figure 3 shows the first order loop filter integrator.…”

“…Several existing techniques in ΔΣ ADC architecture reduce the power consumption at the cost of speed [25][26][27][28][29]. Hence the performance of ADC can be improved by transferring the signal processing task to digital domain and by applying proper scaling methodology.…”

“…Table 1 shows performance comparision of proposed delta-sigma ADC with prior works [39][40][41][42][43][44]. The power of 12-bit incremental delta-sigma ADC is reduced up to 65% when compared with conventional ADCs [45][46][47].…”