On the speedup required for work-conserving crossbar switches

Krishna, P.; Patel, N.S.; Charny, A.; Simcoe, Robert J.

doi:10.1109/49.772435

Cited by 100 publications

(54 citation statements)

References 15 publications

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“…To cope with the segmentation overhead and the scheduler inefficiencies of unbuffered crossbars, switches and routers use internal speedup [5] -often by a factor of two to three in commercial products. 1 This speedup is very expensive: today, the crossbar chip power consumption is often the limiting factor for the aggregate performance of the system, and power consumption translates directly into (mostly I/O) throughput.…”

Section: Introductionmentioning

confidence: 99%

Variable packet size buffered crossbar (CICQ) switches

Katevenis

Passas

Simos

et al. 2004

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

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Abstract-One of the most widely used architectures for packet switches is the crossbar. A special version of a it is the buffered crossbar, where small buffers are associated with the crosspoints. The advantages of this organization, when compared to the unbuffered architecture, is that it needs much simpler and slower scheduling circuits, while it can shape the switched traffic according to a given set of Quality of Service (QoS) criteria in a more efficient way. Furthermore, by supporting variable length packets throughout a buffered crossbar: a) there is no need for segmentation and reassembly circuits, b) no internal speedup is necessary, and c) synchronization between the input and output clock domains is simplified. In this paper we present an architecture, a hardware implementation analysis, and a performance evaluation of such a buffered crossbar. The proposed organization is simple, yet powerful and can be easily implemented using today's technologies. Our evaluation shows that it outperforms most of the existing packet switch architectures, while its hardware cost is kept to a minimum.

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Section: Introductionmentioning

confidence: 99%

Variable packet size buffered crossbar (CICQ) switches

Katevenis

Passas

Simos

et al. 2004

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

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“…Consider the following definition, which was first proposed in [12] motivated from the classical queueing theory.…”

Section: Work Conservationmentioning

confidence: 99%

“…Unfortunately the perfect emulation of OQ requires complicated stable-marriage style algorithms which are not feasible to implement at a very high-speed. In [12] it was shown that simpler scheduling algorithms can achieve the same performance of an OQ switch in terms of average delay.…”

Section: Introductionmentioning

confidence: 99%

Delay bounds for combined input–output switches with low speedup

Giaccone

Leonardi

Prabhakar

et al. 2004

Performance Evaluation

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“…This problem requires a central scheduler to coordinate the set of input/output pairs (flows, or connections) that will be in the crossbar in each time-slot [1] [2] [3]; this is a complex task that can limit the switch packet rate. Heuristic algorithms that have been adopted today work well only when internal speedup is used to compensate for their scheduling inefficiencies [4]. Because these algorithms operate only on fixed-size units, additional speedup is needed when external packets have variable size, to compensate for segmentation padding.…”

Section: Introductionmentioning

confidence: 99%

Scheduling in switches with small internal buffers

Chrysos

Katevenis

2005

GLOBECOM '05. IEEE Global Telecommunications Conference, 2005.

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Abstract-Unbuffered crossbars or switching fabrics contain no internal buffers, and function using only input (VOQ) and possibly output queues. Schedulers for such switches are complex, and introduce increased delay at medium loads, because they have to admit at most one cell per input and per output, during each time slot. Buffered crossbars, on the other hand, contain sufficient internal buffering (N 2 buffers) to allow independent schedulers to concurrently forward packets to the same output from any number of inputs. These architectures represent the two extremes in a range of solutions, which we examine here; although intermediate points in this range are of reduced practical interest for crossbars, they are nevertheless quite interesting for switching fabrics, and they may be of interest for optical switches. We find that tolerating two cells per-output per timeslot, using small buffers inside the switch or fabric, suffices for independent and efficient scheduling. First, we introduce a novel "request-grant" credit protocol, enabling N inputs to share a small switch buffer. Then, we apply this protocol to a switch with N such buffers, one per output, and we consider the resulting scheduling problem. Interestingly, this looks like unbuffered crossbar schedulers, but it is much simpler because it comprises independent, single-resource schedulers that can be pipelined. We show that individual buffer sizes do not need to grow, neither with switch size nor with propagation delay. Through simulations, we study performance as a function of the number of cells allowed per-output per-time-slot. For one cell, the switch performs very close to the iSLIP unbuffered crossbar with one iteration. For more cells, performance improves quickly; for 12 cells, packet delay under (smooth) uniform load is practically as low as ideal output queueing. Under unbalanced load, throughput is superior to buffered crossbars, due to better buffer sharing.

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On the speedup required for work-conserving crossbar switches

Cited by 100 publications

References 15 publications

Variable packet size buffered crossbar (CICQ) switches

Variable packet size buffered crossbar (CICQ) switches

Delay bounds for combined input–output switches with low speedup

Scheduling in switches with small internal buffers

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