On the use of C++ for system-on-chip design

Verkest, D.; Cockx, J.; Potargent, F.; Jong, Gjalt de; Man, H. De

doi:10.1109/iwv.1999.760470

Cited by 15 publications

(5 citation statements)

References 4 publications

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“…System-level and hardware specification languages are active areas of research. Most approaches are based on programming language and raise the level of abstraction above register transfer level (RTL) into either the architectural and behavioral spaces design [16]- [19]. SpecC [5] and SystemC [4] are approaches that are based on the C/C++ programming languages.…”

Section: B System-level Design and Architecturesmentioning

confidence: 99%

BalBoa: A component-based design environment for system models

Doucet

Shukla

Otsuka

et al. 2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents the BALBOA component composition framework for system-level architectural design. It has three parts: a loosely-typed component integration language (CIL); a set of C++ intellectual property (IP) component libraries; and a set of split-level interfaces (SLIs) to link the two. A CIL component interface can be mapped to many different C++ component implementations. A type-inference system maps all weakly-typed CIL interfaces to strongly typed C++ component implementations to produce an executable architectural model. Thus, this amounts to selecting IP implementations according to a set of connection constraints. The SLIs are used to select, adapt, and validate the implementation types. The advantage of using the CIL is that the design description sizes are much smaller because the runtime infrastructure automatically selects the IP and communication implementations. The type inference facilitates changes by automatically propagating them through the design structure. We show that the inference problem is NP complete and we present a heuristic solution to the problem. We bring forth a number of issues related to the automation of reusable IP composition including type-compatibility checking, split-programming, and introspective composition environment, and demonstrate their utility through design examples. Index Terms-Hardware/software co-design, system-on-chip, embedded systems, hardware description language (HDL), modeling, simulation, design reuse, interface design. I. INTRODUCTION R AISING the abstraction levels at which microelectronic system designs are entered and validated has a direct impact on the design quality and design time [1]. Consequently, recent research efforts in the area have been focused on the specification methodologies and languages for system-level

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Section: B System-level Design and Architecturesmentioning

confidence: 99%

BalBoa: A component-based design environment for system models

Doucet

Shukla

Otsuka

et al. 2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Each model details three aspects of the target systemfunctionality, structure and timing [6]. Figure 1 indicates the design flow of SLOOP.…”

Section: The Sloop Design Processmentioning

confidence: 99%

An object-oriented design process for system-on-chip using UML

Zhu

Matsuda

Kuwamura

et al. 2002

Proceedings of the 15th International Symposium on System Synthesis - ISSS '02

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The object-oriented design process has been a hot topic in software development since it will improve product quality and productivity significantly, which is also a major issue in systemon-chip design. In this paper, a design process is proposed for hardware-software heterogeneous systems by reinforcing parallelism, structure, and timing. The management of design abstraction is also introduced for refinement of hardware. UML is used as a modeling language, and the reinforcement above is gracefully integrated into UML by its extensibility mechanism. An example of architecture exploration and performance analysis is illustrated through the application of the process to an image decoding design.

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“…When taking timing aspects into account during refinement of the system model, some additional primitives are needed to express this kind of behavior. The way time is modeled in the system is similar to the way it is done in TIPSY [5] and POLLS [10]. This is a locally synchronous, globally asynchronous time model; meaning time is supported by having a local time in each process, and a scheduler that synchronizes the advancement of time in the system.…”

Section: T I M E D D a T A M O D E Lmentioning

confidence: 99%

Hardware/software partitioning of embedded system in OCAPI-xl

Vanmeerbeeck

Schaumont

Vernalde

et al. 2001

Proceedings of the Ninth International Symposium on Hardware/Software Codesign - CODES '01

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The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the I-IW / SW partitioning decision needs to be made prior to refining the system description. With OCAPI-xl, we developed a methodology in which the partitioning decision can be made anywhere in the design flow, even just prior to doing code-generation for beth HW and SW. This is made possible thanks to a refinable, implementable, architecture independent system description. The OCAPI-xl model was used to develop a stand alone, networked camera, with onboard GIF engine and network layer.

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On the use of C++ for system-on-chip design

Cited by 15 publications

References 4 publications

BalBoa: A component-based design environment for system models

BalBoa: A component-based design environment for system models

An object-oriented design process for system-on-chip using UML

Hardware/software partitioning of embedded system in OCAPI-xl

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