A high-level concurrent model such as a SystemC transaction-level model can provide early feedback during the exploration of implementation alternatives for state-of-the-art signal processing applications like video codecs on a multiprocessor platform. However, the creation of such a model starting from sequential code is a time-consuming and error-prone task. It is typically done only once, if at all, for a given design. This lack of exploration of the design space often leads to a suboptimal implementation. To support our systematic C-based design flow, we have developed a tool to generate a concurrent SystemC transaction-level model for user-selected task boundaries. Using this tool, different parallelization alternatives have been evaluated during the design of an MPEG-4 simple profile encoder and an embedded zero-tree coder. Generation plus evaluation of an alternative was possible in less than six minutes. This is fast enough to allow extensive exploration of the design space.

The design of increasingly complex and concurrent multimedia systems requires a description at a higher abstraction level. Using an appropriate model of computation helps to reason about the system and enables design time analysis methods. The nature of multimedia processing matches in many cases well with cyclo-static dataflow (CSDF), making it a suitable model. However, channels in an implementation often use for cost reasons a kind of shared buffer that cannot be directly described in CSDF. This paper shows how such implementation specific aspects can be expressed in CSDF without the need for extensions. Consequently, the CSDF graph remains completely analyzable and allows reasoning about its temporal behavior. The obtained relation between model and implementation enables a buffer capacity analysis on the model while assuring the throughput of the final implementation. The capabilities of the approach are demonstrated by analyzing the temporal behavior of an MPEG-4 video encoder with a CSDF graph.

A virtual prototype combines a hardware model with hardware/software cosimulation to support the development and debugging of embedded software before a hardware prototype is available. Existing techniques for hardware/software cosimulation execute the software either on an instruction set simulator for accuracy, or on the simulator host processor for increased performance. On the host processor, timing is either completely ignored or approximated using timing annotations in the code. Although preemption (interrupts) can strongly influence the timing, it is rarely modeled to avoid a performance degrading that would make the virtual prototype unusable, especially for real time signal processing software simulations which is already time consuming as such.We propose a technique to accurately model preemption and its effect on software timing in a simulation based on host code execution. Our technique has been implemented in the TIPSY C++ library for executable system modeling; pseudo C-code for this implementation with several optimizations is included in this paper. With this implementation, a preemptive scheduler model can easily be created or taken from a library and inserted in a system model without changing the original code to observe the effect of preemption on the system behavior.0-7695-0668-2/00 $10.00 ã 2000 IEEE

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