2018
DOI: 10.1063/1.5036984
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On the validity and applicability of models of negative capacitance and implications for MOS applications

Abstract: The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the framework of a FE polarization switching model. However, there is a large amount of literature attributing this effect to a stabilization of quasi-static (QS) negative capacitance (NC) in the FE. The technological implications of a stabilized non-switching (NS) QSNC model vs a FE sw… Show more

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Cited by 37 publications
(24 citation statements)
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“…However, physical understanding of NC effects is still under intensive debate [25][26][27][28][29][30][31][32][33][34][35][36] . Experimentally observed NC effects are different from each other, and also from the concepts initially proposed.…”
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confidence: 99%
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“…However, physical understanding of NC effects is still under intensive debate [25][26][27][28][29][30][31][32][33][34][35][36] . Experimentally observed NC effects are different from each other, and also from the concepts initially proposed.…”
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confidence: 99%
“…Alternative explanations for the capacitance enhancement and transient NC effects in FE/PE stacks have been also proposed [25][26][27][28][29][30][31] . For example, a feasibility of capacitance enhancement is explainable from a strong coupling between FE and PE layers [25][26][27] , while the transient NC is understandable from the viewpoints of overshoot in voltage supply or slower speed of charge compensation relative to polarization switching in FE-CAP [28][29][30][31] . In fact, it has been argued that NC region of FE material is intrinsically unstable or even impossible 32,33 .…”
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confidence: 99%
“…Besides improving the sub-threshold slope significantly, the inclusion of a Ferroelectric layer of thickness of 4 nm in the gate stack will also eliminate the tunneling current through the gate oxide [6]. The Ferroelectric material has been deposited on the existing High-k gate stack, with the Ferroelectric material parameters reported by Agarwal et al [26] used for the simulation of the electrostatics of the Metal-Ferroelectric-Insulator-Semiconductor (MFIS) FET structure, which is found to be more practical compared to the Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) structure [27]. The use of a Ferroelectric material in the gate stack of a short channel MOSFET has been reported to result in Drain induced barrier raise (DIBR) [28].…”
Section: Incorporation Of a Ferroelectric Materials Based Gate Stack ...mentioning
confidence: 99%
“…A second strategy exploits a positive feedback mechanism that amplifies the electrostatic control of the gate over the channel surface potential, such as in the nanoelectromechanical FET [11][12][13] and the steep-slope ferroelectric FET (SS-FeFET) [14][15][16][17] . In a SS-FeFET, the internal voltage amplification is realized either by means of abrupt (non-stabilized SS-FeFET) [18][19][20][21][22][23] , or gradual polarization switching (stabilized SS-FeFET) [24][25][26][27][28][29][30][31] of the ferroelectric.…”
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confidence: 99%
“…The importance of analyzing the appropriate thermodynamic potential cannot be understated: a thermodynamic equilibrium analysis based on an inappropriate potential is at risk of producing unphysical results. In the vast majority of works published today, the Gibbs free energy 21,[38][39][40][41][42][43][44] or (though less frequently) the Helmholtz free energy 27,45,46 is used. However, a formal justification has never been provided.…”
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confidence: 99%