On the ZBDD-based nonenumerative path delay fault coverage calculation

Kocan, Fatih; Güneş, Mehmet Hadi

doi:10.1109/tcad.2005.850851

Cited by 6 publications

(16 citation statements)

References 7 publications

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“…The work of [25] proposed a more compact path representation compared to the one in [36]. Specifically, [25] shows that all paths can be represented using one ZDD variable per primary input and one ZDD variable per circuit branch line (referred to as primary lines). This approach is suitable for the PDF test grading problem and it constructs ZDDs with smaller size that those in [36].…”

Section: Zdd-based Path Representationmentioning

confidence: 99%

“…A number of previous works considering applications in EDA [8,25,30,32,36,40,44] have shown that paths can be represented compactly using Zero-Suppressed Ordered Binary Decision Diagrams (ZDDs) [31], a variant of Binary Decision Diagrams [6]. This representation is very important since the performance of the basic operations on a ZDD is linear to its size.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, we present new experimental results that demonstrate that the proposed static ordering method is superior to a dynamic approach. Finally, one of the numerous possible applications of the presented theoretical result, that of Path Delay Fault (PDF) test grading, is used to demonstrate the impact of the proposed variable ordering on the method of [36] and its later extension in [25].…”

Section: Introductionmentioning

confidence: 99%

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Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

Neophytou

Michael

2018

J Electron Test

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The efficient representation and manipulation of a large number of paths in a Directed Acyclic Graph (DAG) requires the usage of special data structures that may become of exponential size with respect to the size of the graph. Several methodologies targeting Electronic Design Automation problems such as timing analysis, physical design, verification and testing involve path representation and necessary manipulation. Previous works proposed an encoding using Zerosuppressed Binary Decision Diagrams (ZDDs), which has been shown experimentally to cope well when representing structural or logical paths in VLSI circuits. However, it is well known that the ordering of the variables in a ZDD highly affects its size and, therefore, the efficiency of the methodologies utilizing these data structures. In this work, we show that using a reverse topological order for the ZDD variables bounds the number of nodes in the ZDD representing structural paths to the number of edges in the DAG considered, hence, making the ZDD size linear to the DAG's size. This result, supported here both theoretically and experimentally, is very important as it can render methodologies with questionable scalability applicable to larger industrial designs. We demonstrate the applicability of

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Section: Zdd-based Path Representationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

Neophytou

Michael

2018

J Electron Test

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“…It is shown in [7] that the problem of obtaining exact coverage is NP-hard. References [8]- [10] generally employ binary decision diagrams (or variants thereof). However, binary-decision diagram are known to be memory-intensive on certain designs.…”

Section: Introductionmentioning

confidence: 99%

Adapting an Implicit Path Delay Grading Method for Parallel Architectures

Lenox

Tragoudas

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault (PDF) coverage estimates, especially as a subroutine for automatic test pattern generation and timing analysis solutions. A parallel adaptation of an established framework for implicit PDF grading on with a general-purpose computing on graphics processing units (GPU) implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50× speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200× speedup is observed against a single-threaded, more complex version in the framework which grades more faults.

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“…[8] has shown that problem of obtaining exact coverage is NP-hard. Work in exact heuristics [9,10,11] that employ binary decision diagrams (or variants thereof) are memory-intensive on certain designs, while approximate heuristics [12,13,8,14, 2] must pay additional time penalties if more accuracy is required. If it is desired to use these path coverage estimates in a larger algorithm (such as test pattern generation or timing analysis) as a subroutine, such penalties are unacceptable.…”

Section: Introductionmentioning

confidence: 99%

A novel parallel adaptation of an implicit path delay grading method

Lenox

Tragoudas

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit path delay fault grading on with a GPGPU implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50x speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200x speedup is observed against a single-threaded, more complex version in the framework which grades more faults.

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On the ZBDD-based nonenumerative path delay fault coverage calculation

Cited by 6 publications

References 7 publications

Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

Adapting an Implicit Path Delay Grading Method for Parallel Architectures

A novel parallel adaptation of an implicit path delay grading method

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