On using SAT to ordered escape problems

Abstract

Routing for high-speed boards is largely a timeconsuming manual task today. The ordered escape routing problem is one of the key problems in board-level routing, and Boolean Satisfiability (SAT) based approach [1] is the only solution to this problem so far. In this paper, we first solve the major deficiency of the original SAT formulation so that the escape problem is completely resolved. Then we propose two techniques to extend SAT approach for large-scale problems. Experimental results on industrial benchmarks show that our methods perform well in terms of both speed and routability.

Advances in PCB Routing

“…However, they also proposed a partition technique to decompose a large problem into smaller problems, which could significantly reduce the runtime. In a later paper [16], Luo and Wong extended their router to handle cyclic ordering and pin clustering. Because their router is very powerful in solving small but difficult problems, they also propose to use their router to rip-up and reroute a small region where other heuristic-based routers fail to complete the routing.…”

Length-constrained escape routing of differential pairs

“…Since the use of differential pairs is not avoidable, the assignment of differential pairs must be considered during pin assignment [9]. Although the escape routing problem in PCB designs has been well studied, previous works [1][2][3][4][5][6][7][8] did not consider the escape routing of differential pairs in PCB designs. For board-level routing, the routing of differential pairs has been considered in chip-package-board codesign by Fang et al [10].…”

“…Even though no cycle exists in a routing graph, the approach cannot find the routing solution where detour is needed for the resource conflict. For ordered escape routing with floating pins, the SATbased approaches [6][7] are proposed to exactly complete the ordering escape routing based on the Boolean satisfiability. Although the SAT-based approaches perform well in routability, the proposed approaches do not consider the larger capacity between any pair of adjacent pins, i.e., it is assumed that the capacity between any pair of adjacent pins is 1.…”

Escape Routing for Staggered-Pin-Array PCBs

“…The objective of this problem is to route nets from pins to the boundary of a component. According to the demanded ordering of the escaped pins in the component boundary, the escape routing problem can be classified into three types [2]: unordered escape routing [3]- [11], ordered escape routing [12], [13], and simultaneous escape routing [14]- [16]. Unordered escape routing routes nets without any ordering constraint along the boundary of a component, while ordered escape routing needs to conform to an ordering constraint along the boundary of a component.…”