On zero clock skew hold time failure in scan test

Process variability becomes prominent for circuits using nanometer manufacturing technology. With aggressive voltage scaling, unexpected failures occur due to excessive timing variation. Yield, number of components, and process variability are intrinsically linked. In this paper, we study the setup and hold time definition, margin, and characterization methodology. A new statistical margin quantifying methodology, setup and hold time definition and characterization methodology are proposed.

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A new statistical setup and hold time definition

Bai

Patel

Zhang

2012

2012 IEEE International Conference on IC Design &Amp; Technology

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On zero clock skew hold time failure in scan test

Cited by 1 publication

References 15 publications

A new statistical setup and hold time definition

A new statistical setup and hold time definition

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