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The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that we have developed to enable on-chip at-speed testing of crosstalk defects in System-on-Chip interconnects. The self-test methodology is based on the Maximal Aggressor Fault Model [13], that enables testing of the interconnect with a linear number of test patterns. To enable self-testing of the interconnects, we have designed efficient on-chip test generators and error detectors to be embedded in necessary cores; while the test generators generate test vectors for crosstalk faults, the error detectors analyze the transmission of the test sequences received from the interconnects, and detect any transmission errors. We have also designed test controllers to initiate and manage test transactions by activating the appropriate test generators and error detectors, and having error diagnosis capability. We have developed, simulated, and synthesized parameterized HDL models of the selftest structures. We have applied the self-test methodology to test crosstalk defects in the buses of a DSP chip. Using a new highlevel crosstalk simulation technique, we have validated the selftest methodology, including the self-test structures inserted in the DSP chip. z z z z z z Figure 1 -(a) Glitch , (b) Delay, and (c) Oscillations

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Almost by definition, well-tuned digital circuits have a large number of equally critical paths, which form a so-called "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, model-to-hardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater. Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertainty-aware" mode has been implemented and applied to several high-performance microprocessor macros. Numerical results are included.

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