Onboard FPGA-based SAR processing for future spaceborne systems

Le, Calvin; Chan, S.; Cheng, Fan‐Tien; Fang, Wai-Chi; Fischman, M.A.; Hensley, S.; Johnson, Rob; Jourdan, M.; Marina, M.; Parham, B.; Rogez, F.; Rosen, P. A.; Shah, Biren; Taft, S.

doi:10.1109/nrc.2004.1316388

Cited by 35 publications

(17 citation statements)

References 4 publications

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“…Recording and Processing System time SAR data processing is commonly implemented by properly sub-divide the SAR processing task into multiple sessions and realized through multiple DSPs [4] or FPGAs [5].…”

Section: Fig 2 Block Diagram Of Enhanced Uavsar Datamentioning

confidence: 99%

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A new data acquisition and processing system for UAVSAR

Lim

Chua

et al. 2011

IEICE Electron. Express

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Synthetic Aperture Radar (SAR) is widely known as a high resolution imaging system in microwave remote sensing. Large number of frequency-modulated received echoes must be acquired in real time. A typical SAR data acquisition unit (DAQ) involves high speed analog-to-digital conversion, front-end pre-processing, and data recording. Subsequent processes consist of computationally intensive digital signal processing for image formation. In this paper, an efficient data acquisition and SAR processing method is proposed. It is based on a modified discrete Fourier Transform algorithm, which requires lesser system's computational load as compared to conventional Fast Fourier Transform. The proposed system has been implemented on an UAVSAR (Unmanned Aerial Vehicle SAR) and the flight tests have shown promising results for real-time imaging.

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Section: Fig 2 Block Diagram Of Enhanced Uavsar Datamentioning

confidence: 99%

“…Conventional designs use high speed dedicated chipsets, such as the digital signal processor (DSP) [4] and the field-programmable gate array (FPGA) [5] for UAVSAR system. However, there exist certain drawbacks in these designs, such as no real time image output and long processing time.…”

Section: Introductionmentioning

confidence: 99%

A new data acquisition and processing system for UAVSAR

Lim

Chua

et al. 2011

IEICE Electron. Express

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“…An experimental SAR processing system based on VLSI/SOC hardware has been proposed [22]. A fault-tolerant FPGA (Xilinx Virtex-II Pro)-based architecture has been proposed and tested using the SIR-C data [23,24]. The University of Florida developed a high-performance space computing framework based on a hardware/software interface in 2006 [25].…”

Section: Introductionmentioning

confidence: 99%

A Multi-mode SAR Imaging Chip based on a Dynamically Reconfigurable SoC Architecture Consisting of Dual-operation Engines and Multilayer Switching Network

Long¹,

Yang²,

B³

et al. 2018

Preprint

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With the development of satellite load technology and very-large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. Limited by severe size, weight, and power consumption constraints, a key challenge of on-board SAR imaging system design is to achieve high real-time processing performance. In addition, with the rise of multi-mode SAR applications, the reconfiguration of the on-board processing system is beginning to receive widespread attention. This paper presents a multi-mode SAR imaging chip with SoC architecture based on the reconfigurable double-operation engines and multilayer switching network. We decompose the commonly used extend chirp scaling (CS) SAR imaging algorithm into 8 types of double-operation engines according to the computing orders, and design a three-level switching network to connect these engines for data transition. The CPU is responsible for engine scheduling based on data flow driven with instructions to implement each part of the CS algorithm. Thus, multi-mode floating-point SAR imaging processing can be integrated into a single Application-Specific Integrated Circuit (ASIC) chip instead of relying on distributed technologies. As a proof of concept, a prototype measurement system with chip-included board is implemented, and the performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. A chip requires 9.2 s, 50.6 s and 7.4 s for a stripmap with 16,384×16,384 granularity, multi-channel stripmap with 65.536×8192 granularity and multi-channel scan mode with 32,768×4096 granularity and 6.9 W for the system hardware to process the SAR raw data.

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“…However, it has a high error-ratio by cutting out Least Significant Bits (LSBs) in computation. While nowadays, more and more advanced applications such as Synthetic Aperture Radar (SAR) [7] or medical image processing like Fourier-Domain Optical Coherence Tomography (FD-OCT) [8], require not only a high precision but also a wide dynamic range of data. As a result, the floating point becomes an essential requirement for computing large points of FFT.…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed High-Accuracy 2048-Point FFT Using Single-Precision Floating-Point Adaptive Cordic on Fpga

2018

JST

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In this paper, hardware design of a Fast Fourier Transform (FFT) core using Single-precision Floating-point Adaptive CORDIC is implemented on Altera Stratix IV FPGA. With FFT implementation, CORDIC is utilized for reducing the speed drawback of complex multiplication and the adaptive algorithm is proposed to decrease the iterations of conventional CORDIC. The experimental results of Adaptive CORDIC and 2048-point Radix-2 Multi-path Delay Commutator FFT designs are built and verified based on three kinds of Look-up Table that cost 16, 8 and 4 constant angles. As experimental results, there is a resource equivalence while it has a trade-off between speed performance and accuracy. In comparison, an adaptive CORDIC core based on Look-up Table of 16 constant angles, and 2048-point Radix-2 Multi-path Delay Commutator Fast Fourier Transform based on Adaptive CORDIC using Look-up Table of 16 constant angles are well responding to resource optimization, high-speed performance and high-accuracy of computations.

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Onboard FPGA-based SAR processing for future spaceborne systems

Cited by 35 publications

References 4 publications

A new data acquisition and processing system for UAVSAR

A new data acquisition and processing system for UAVSAR

A Multi-mode SAR Imaging Chip based on a Dynamically Reconfigurable SoC Architecture Consisting of Dual-operation Engines and Multilayer Switching Network

Design of a High-Speed High-Accuracy 2048-Point FFT Using Single-Precision Floating-Point Adaptive Cordic on Fpga

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