1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC
DOI: 10.1109/isscc.1996.488616
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One-transistor-cell multiple-valued CAM for a collision detection VLSI processor

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Cited by 8 publications
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“…Our proposed design is significantly superior to CAM cell designs based on single flash memory transistors,. [16][17][18] First, the flash memory-based CAM design is a serial design, as the match or mismatch operation is performed bit-by-bit. To search a CAM word with N cells, it would require 2 N cycles without pipelining or N þ 1 cycles with pipelining, which significantly degrades the search speed of CAMs.…”
Section: Introductionmentioning
confidence: 99%
“…Our proposed design is significantly superior to CAM cell designs based on single flash memory transistors,. [16][17][18] First, the flash memory-based CAM design is a serial design, as the match or mismatch operation is performed bit-by-bit. To search a CAM word with N cells, it would require 2 N cycles without pipelining or N þ 1 cycles with pipelining, which significantly degrades the search speed of CAMs.…”
Section: Introductionmentioning
confidence: 99%
“…Publisher Item Identifier S 0018-9200(96)07589-0. Our design also stands in contrast to the CAM cell array using floating gate transistors described by T. Hanyu et al in [6] and [7]. While LSI's based on such multivalued arrays have the great advantage of higher density, they would be hard to implement: the complicated multivalued logic they require would mean that their active operational margins would be smaller than normal binary flash memories and insufficient for stable operations.…”
Section: Introductionmentioning
confidence: 99%