OO-VHDL. Object-oriented extensions to VHDL

Swamy, Sneha; Molin, Adam; Covnot, B.

doi:10.1109/2.467587

Cited by 51 publications

(23 citation statements)

References 2 publications

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“…Previous efforts tried to develop object-oriented extensions of VHDL [42,43], to encapsulate VHDL by an object-oriented reuse environment [44], or to apply software objectoriented languages such as Cþþ or Java to model hardware. However, object-oriented hardware modeling became a reality only in the context of system-level design, with the emergence of SystemC [31].…”

Section: Ip Derivationmentioning

confidence: 99%

Strategies for the integration of hardware and software IP components in embedded systems-on-chip

Wagner¹,

Cesario²,

Carro³

et al. 2004

Integration

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Section: Ip Derivationmentioning

confidence: 99%

Strategies for the integration of hardware and software IP components in embedded systems-on-chip

Wagner¹,

Cesario²,

Carro³

et al. 2004

Integration

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“…Objective VHDL combines the structural object approach [14] with the type object approach [12]. Both language extensions have shown their suitability for hardware design.…”

Section: Objective Vhdlmentioning

confidence: 99%

“…In [14] some kind of identifier for an entity object, called a handle which can be exchanged among entities, is proposed. If an object has the handle of another object, the handle can be used to address the other object to pass a message.…”

Section: Communication Pathwaysmentioning

confidence: 99%

“…The Vista approach [14] introduces a new design unit called Entity Object (EO) which is based on the VHDL entity and it's architecture. In addition to the entity the EO may contain method specifications called operation specifications.…”

Section: Other Oo-vhdl Approachesmentioning

confidence: 99%

“…During the last years several proposals for an objectoriented extension to VHDL have been made [1][2] [4][12] [14]. All the proposals need to define message passing to be object-oriented.…”

Section: Other Oo-vhdl Approachesmentioning

confidence: 99%

See 2 more Smart Citations

A flexible message passing mechanism for Objective VHDL

Putzke-Roming¹,

Radetzki²,

Nebel³

Proceedings Design, Automation and Test in Europe

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When defining an object-oriented extension to VHDL, the necessary message passing is one of the most complex issues and has a large impact on the whole language. This paper identifies the requirements for message passing suited to model hardware and classifies different approaches. To allow abstract communication and reuse of protocols on system level, a new, flexible message passing mechanism proposed for Objective VHDL 1 will be introduced.

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VHDL generation from SDL specifications

Daveau¹,

Marchioro²,

Valderrama³

et al. 1997

Hardware Description Languages and Their Applications

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The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powerful communication model which enable the representation in a synthesis oriented manner of most communication schemes. This intermediate form allows the refinement of the system in order to obtain the desired solution. The main refinement step, called communication synthesis, is aimed at fixing the protocol and the interface used by the different processes to communicate. The refined specification is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility of our approach through two SDL to VHDL translation examples.

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OO-VHDL. Object-oriented extensions to VHDL

Cited by 51 publications

References 2 publications

Strategies for the integration of hardware and software IP components in embedded systems-on-chip

Strategies for the integration of hardware and software IP components in embedded systems-on-chip

A flexible message passing mechanism for Objective VHDL

VHDL generation from SDL specifications

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