Opal: A Centralized Memory Manager for Investigating Disaggregated Memory Systems

Kommareddy, Vamsee Reddy; Hughes, Clayton; Hammond, Simon David; Awad, Amro

doi:10.2172/1467164

Cited by 7 publications

(6 citation statements)

References 6 publications

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“…SST includes multiple (swappable) simulation modules for various components. A module called Opal [23] has been developed in SST to simulate centralized memory manager for disaggregated memory model. [14] leblancbig.pnt miniFE [18] -nx 140 -ny 140 -nz 140 NAS:IS [5] class C…”

Section: Discussionmentioning

confidence: 99%

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Page migration support for disaggregated non-volatile memories

Kommareddy

Hammond

Hughes

et al. 2019

Proceedings of the International Symposium on Memory Systems

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As demands for memory-intensive applications continue to grow, the memory capacity of each computing node is expected to grow at a similar pace. In high-performance computing (HPC) systems, the memory capacity per compute node is decided upon the most demanding application that would likely run on such system, and hence the average capacity per node in future HPC systems is expected to grow significantly. However, since HPC systems run many applications with different capacity demands, a large percentage of the overall memory capacity will likely be underutilized; memory modules can be thought of as private memory for its corresponding computing node. Thus, as HPC systems are moving towards the exascale era, a better utilization of memory is strongly desired. Moreover, upgrading memory system requires significant efforts. Fortunately, disaggregated memory systems promise better utilization by defining regions of global memory, typically referred to as memory blades, which can be accessed by all computing nodes in the system, thus achieving much better utilization. Disaggregated memory systems are expected to be built using dense, power-efficient memory technologies. Thus, emerging nonvolatile memories (NVMs) are placing themselves as the main building blocks for such systems. However, NVMs are slower than DRAM. Therefore, it is expected that each computing node would have a small local memory that is based on either HBM or DRAM, whereas a large shared NVM memory would be accessible by all nodes. Managing such system with global and local memory requires a novel hardware/software co-design to initiate page migration between global and local memory to maximize performance while enabling access to huge shared memory. In this paper we provide support to migrate pages, investigate such memory management aspects and the major system-level aspects that can affect design decisions in disaggregated NVM systems

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Section: Discussionmentioning

confidence: 99%

“…Centralized memory manager is required to maintain and allocate decoupled centralized memory. We used Opal [23] from SST [35] as a centralized memory manager. Opal is responsible for allocating memory to all the nodes without any conflicts.…”

Section: Performing Page Migrationmentioning

confidence: 99%

Page migration support for disaggregated non-volatile memories

Kommareddy

Hammond

Hughes

et al. 2019

Proceedings of the International Symposium on Memory Systems

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“…SST includes multiple simulation modules for various components. To evaluate FAM architectures a FAM manager (memory broker), Opal [30], was developed in SST. We modified SST memory management unit, Samba [5] and Opal [30] modules to model our design.…”

Section: Methodsmentioning

confidence: 99%

“…To evaluate FAM architectures a FAM manager (memory broker), Opal [30], was developed in SST. We modified SST memory management unit, Samba [5] and Opal [30] modules to model our design. We modelled an STU component in SST to translate node addresses to fabric addresses and to verify FAM accesses.…”

Section: Methodsmentioning

confidence: 99%

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DeACT: Architecture-Aware Virtual Memory Support for Fabric Attached Memory Systems

Kommareddy¹,

Hughes²,

Hammond³

et al. 2020

Preprint

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The exponential growth of data has driven technology providers to develop new protocols, such as cache coherent interconnects and memory semantic fabrics, to help users and facilities leverage advances in memory technologies to satisfy these growing memory and storage demands. Using these new protocols, fabric-attached memories (FAM) can be directly attached to a system interconnect and be easily integrated with a variety of processing elements (PEs). Moreover, systems that support FAM can be smoothly upgraded and allow multiple PEs to share the FAM memory pools using well-defined protocols. The sharing of FAM between PEs allows efficient data sharing, improves memory utilization, reduces cost by allowing flexible integration of different PEs and memory modules from several vendors, and makes it easier to upgrade the system.One promising use-case for FAMs is in High-Performance Compute (HPC) systems, where the underutilization of memory is a major challenge. However, adopting FAMs in HPC systems brings new challenges. In addition to cost, flexibility, and efficiency, one particular problem that requires rethinking is virtual memory support for security and performance. To address these challenges, this paper presents decoupled access control and address translation (DeACT), a novel virtual memory implementation that supports HPC systems equipped with FAM. Compared to the state-of-the-art two-level translation approach, DeACT achieves speedup of up to 4.59x (1.8x on average) without compromising security.

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