Open-Circuit Switching Fault Analysis and Tolerant Strategy for Dual-Active-Bridge DC–DC Converter Considering Parasitic Parameters

Wang, Yu; Guan, Yuanpeng; Molinas, Marta; Fosso, Olav Bjarte; Hu, Wang; Zhang, Yun

doi:10.1109/tpel.2022.3193872

Cited by 11 publications

(1 citation statement)

References 33 publications

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“…Hitherto, Rastogi et al have identified the failed transistor for the two-level (2L) 3P DAB by evaluating the pattern of DC bias voltage [25]. The 3L-NPC converter generates a similar DC bias voltage for open switch failure across mid-MOSFETs, which makes it difficult to identify the failed MOSFET [24] - [26]. Therefore, the mid-point voltage has been utilized as a diagnosis criterion to identify the location of a switch failure in the triple-phase shift converter [27]- [29].…”

Section: Introductionmentioning

confidence: 99%

Overvoltage Protection of Series-Connected 10kV SiC MOSFETs Following Switch Failures in MV 3L-NPC Converter for Safe Fault Isolation and Shutdown

Parashar,

Isik,

Kolli

et al. 2024

IEEE Access

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This paper presents a design methodology for overvoltage protection across 10kV SiC MOSFETs during turn-off after switch failure in a MV SST Power Conditioning System (PCS) enabled by a cascaded Three-Phase (3P) Three-level (3L) Neutral Point Clamped (NPC) Active Front-End Converter (AFEC) and Dual Active Bridge (DAB) using series-connected 10kV SiC MOSFETs and 10kV SiC JBS diodes. The methodology uses an active voltage clamp at the gate terminal and desat detection technique to identify abrupt open and turn-on switch failures across series-connected 10kV SiC MOSFETs. The analytical model estimates over-current time and turn-off voltage transition by considering bus bar inductance, device base plate capacitance and common mode (CM) choke tied between the heat sink and midpoint of the DC link capacitor. The transition model is used to evaluate the turn-off timing for series-connected MOSFETs, snubber resistors, snubber capacitors, and gate resistors to avoid MOSFET overvoltage during converter shutdown, without affecting the voltage balancing and efficiency during normal operation. The MOSFET turn-off transition during the shutdown has been verified in the Saber RD simulation using the validated Saber RD MAST model of 10kV SiC MOSFETs and 10kV SiC JBS diodes at 13.8kV AC/24kV DC level. The fault isolation and MV SST PCS shutdown have been verified in a real-time environment using HIL setup with Xilinx FPGAs and RTDS, at 13.8kV AC/24kV DC link under PCS operating conditions. The normal operation of 3L-NPC pole hardware with modified snubber resistors, snubber capacitors, and gate resistors is verified by experiments conducted at 7kV DC, 10A load current.

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