OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters

Burgio, Paolo; Marongiu, Andrea; Heller, Dominique; Coussy, Philippe; Benini, Luca

doi:10.1109/dsd.2012.97

Cited by 13 publications

(12 citation statements)

References 13 publications

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“…We demonstrate our approach on an OpenMP-enabled SystemCbased virtual platform for on-chip multi-core shared-memory clusters with hardware accelerators [27]. Table I summarizes the architectural parameters.…”

Section: Resultsmentioning

confidence: 99%

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

Rahimi¹,

Marongiu²,

Gupta³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floatingpoint units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an applicationdriven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

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Section: Resultsmentioning

confidence: 99%

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

Rahimi¹,

Marongiu²,

Gupta³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Self Cite

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“…As we extend the STMicroelectronics P2012 cluster with tightly L1-coupled HW accelerators, our architectural template is similar to that used in Burgio et al [8] and Dehyadegari et al [17], but in our case it was implemented in a real, complete many-core platform. Moreover, contrarily to previous work in this category of accelerators, we propose a full-fledged flow that allows fast design exploration of heterogeneous clusters, with semi-automatic generation of HWPEs and estimation of power and area consumption based on RTL synthesis results.…”

Section: Related Workmentioning

confidence: 96%

“…Cong et al [10] also tackle the utilization wall by developing a heterogeneous multi-core architecture with shared-memory accelerators; their HW IPs communicate by means of shared L2 caches, accessible through NoC nodes. Previous work by our group (Burgio et al [8], Dehyadegari et al [16,17], Conti et al [11]) considers a tightly-coupled multi-core based on RISC32 cores sharing a L1 scratchpad and extend it with hardware processing units (HWPUs). HWPUs are managed by the software through an OpenMPbased programming model designed to mix parallelization and acceleration.…”

Section: Related Workmentioning

confidence: 99%

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti

Marongiu

Pilkington

et al. 2015

J Sign Process Syst

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The end of Dennardian scaling in advanced technologies brought about new architectural templates to overcome the so-called utilization wall and provide Moore's Law-like performance and energy scaling in embedded SoCs. One of the most promising templates, architectural heterogeneity, is hindered by high cost due to the design space explosion and the lack of effective exploration tools. Our work provides three contributions towards a scalable and effective methodology for design space exploration in embedded MC-SoCs. First, we present the He-P2012 architecture, augmenting the state-of-art STMicroelectronics P2012 platform with heterogeneous shared-L1 coprocessors called HW processing elements (HWPE). Second, we propose a novel methodology for the semi-automatic definition and instantiation of shared-memory HWPEs from a C source, supporting both simple and structured data types. Third, we demonstrate that the integration of HWPEs can provide significant performance and energy efficiency benefits on a set of benchmarks originally developed for the homogeneous P2012, achieving up to 123x speedup on the accelerated code region (∼98 % of Amdahl's law limit) while saving 2/3 of the energy.

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“…Burgio et al [9] refer to a similar architecture and focus on the programming model to support it. The IPs are described with simple annotations of the software C code through the use of an extension to the OpenMP standard.…”

Section: Related Workmentioning

confidence: 98%

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Conti¹,

Marongiu²,

Benini³

2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where lowlatency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed.

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OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters

Cited by 13 publications

References 13 publications

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

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