Operation Voltage Dependence of Memory Cell Characteristics in Fully Depleted Floating-Body Cell

Shino, T.; Ohsawa, Takashi; Higashi, Taneaki; Fujita, Katsushi; Kusunoki, N.; Minami, Y.; Morikado, M.; Nakajima, H.; Inoh, K.; Hamamoto, T.; Nitayama, A.

doi:10.1109/ted.2005.856808

Cited by 23 publications

(16 citation statements)

References 8 publications

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“…(2), the target of DV th and r V th are 0.40 V and 22 mV, respectively. The signal of FBC can be written as the following formula [11]:…”

Section: Estimation Of the Scalability Of Fbcmentioning

confidence: 99%

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Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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“…(2), the target of DV th and r V th are 0.40 V and 22 mV, respectively. The signal of FBC can be written as the following formula [11]:…”

Section: Estimation Of the Scalability Of Fbcmentioning

confidence: 99%

“…Some kinds of capacitor-less DRAM cell have been proposed and developed [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Floating body cell (FBC) is a promising candidate in view of its simple structure and scalability.…”

Section: Introductionmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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“…Despite this memory cell is nothing but a regular FDSOI MOSFET without MSDRAM optimization, very high current margins (I 1 -I 0 > 180 µA/µm) can be obtained, surpassing other advanced 1T-DRAM candidates (2)(3)(4)(5)(6)(7)(8). Fig.…”

Section: Msdram Devicementioning

confidence: 99%

(Invited) Special Memory Mechanisms in SOI Devices

Cristoloveanu¹,

Bawedin²,

Navarro³

et al. 2015

ECS Trans.

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Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the 'unified memory' paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our recently proposed concepts (MSDRAM, A2RAM and Z 2 -FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues. Experimental results together with numerical simulations indicate the directions for performance optimization.

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“…5.a) [4,7]. Hence, the junction depletion effect is reduced while a higher current sense margin is achieved.…”

Section: Ecs Transactions 19 (4) 243-256 (2009)mentioning

confidence: 99%

“…In PD SOI MOSFETs, the threshold variation ∆V TH can be approximated by ∆V B x (C D /C OX ) [4], where the body potential variation ∆V B is proportional to the change in ECS Transactions, 19 (4) 243-256 (2009) hole density. This model remains valid for FD SOI MOSFET if the back channel is in accumulation mode.…”

Section: Ecs Transactions 19 (4) 243-256 (2009)mentioning

confidence: 99%