Operational Concepts Of MPEG-4 H.264 For Tactical DOD Applications

Bennett, Bruce; Dee, Christina; Nguyen, Minh-Huy; Hamilton, B.A.

doi:10.1109/milcom.2005.1605679

Cited by 4 publications

(3 citation statements)

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“…High-quality digital video in multimedia devices and video-over-IP networks connected to the Internet are under exponential growth and therefore the demand for applications capable of high dynamic range (HDR) video is accordingly increasing. Some HDR imaging applications include automatic surveillance [1][2][3][4], geospatial remote sensing [5], traffic cameras [6], homeland security [4], satellite based imaging [7][8][9], unmanned aerial vehicles [10][11][12], automotive industry [13], and multimedia wireless sensor networks [14]. Such HDR video systems operating at high resolutions require an associate hardware capable of significant throughput at allowable area-power complexity.…”

Section: Introductionmentioning

confidence: 99%

A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

Madanayake

Cintra²,

Onen³

et al. 2012

IEEE Trans. Circuits Syst. Video Technol.

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An algebraic integer (AI) based time-multiplexed row-parallel architecture and two final-reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8×8 2-D DCT which is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on (i) optimized Dempster-Macleod multipliers and (ii) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on FPGA chip. Six designs, for 4-and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented and measured. The maximum clock rate and block-rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8×307.787≈2.462 GHz if eventually embedded in a real-time video-processing system. The equivalent frame rate is about 1187.35 Hz for the image size of 1920×1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.

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Section: Introductionmentioning

confidence: 99%

A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

Madanayake

Cintra²,

Onen³

et al. 2012

IEEE Trans. Circuits Syst. Video Technol.

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“…The growth of video traffic for live and on-demand content has been a challenging demand in reconnaissance and surveillance applications to provide video streaming with high quality viewing, low bandwidth consumption and low processing complexity, considering video compression algorithms [1][2][3][4]. The general solutions for video compression are proposed in scalable video coding (SVC) [5] and the more recent scalable high efficiency video coding (SHVC) [6] that has been studied extensively over the last several decades and is now supported in several video codecs and standards such as H.264/SVC and H.265/HEVC.…”

Section: Introductionmentioning

confidence: 99%

A framework for super-resolution of scalable video via sparse reconstruction of residual frames

Moghaddam

Azizipour

Vahidian

et al. 2017

MILCOM 2017 - 2017 IEEE Military Communications Conference (MILCOM)

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This paper introduces a framework for superresolution of scalable video based on compressive sensing and sparse representation of residual frames in reconnaissance and surveillance applications. We exploit efficient compressive sampling and sparse reconstruction algorithms to super-resolve the video sequence with respect to different compression rates. We use the sparsity of residual information in residual frames as the key point in devising our framework. Moreover, a controlling factor as the compressibility threshold to control the complexity-performance trade-off is defined. Numerical experiments confirm the efficiency of the proposed framework in terms of the compression rate as well as the quality of reconstructed video sequence in terms of PSNR measure. The framework leads to a more efficient compression rate and higher video quality compared to other state-of-the-art algorithms considering performance-complexity trade-offs.

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“…Video compression systems operating at high frequencies and resolutions require hardware capable of significant throughput with tolerable area and power requirements. Real-time video compression circuits having high numerical accuracy are needed for nextgeneration video [1], coding systems [2,3,7], and retina displays [8].…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA

Rajapaksha

Edirisuriya

Madanayake

et al. 2013

Journal of Electrical and Computer Engineering

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Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.

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Operational Concepts Of MPEG-4 H.264 For Tactical DOD Applications

Cited by 4 publications

References 0 publications

A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

A framework for super-resolution of scalable video via sparse reconstruction of residual frames

Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA

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