Operational stability enhancement of low-voltage organic field-effect transistors based on bilayer polymer dielectrics

Abstract

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Bias‐Stress‐Stable Low‐Voltage Organic Field‐Effect Transistors with Ultrathin Polymer Dielectric on C Nanoparticles

“…Furthermore, and signifi cantly, the bias stress stability is of vital importance for practical applications of OFETs, [20][21][22] but there is a lack of bias stress investigations on low-voltage OFETs. [ 18,19 ] Therefore, it is still challenging to achieve a pinhole-free dielectric layer simultaneously enabling low-voltage operation, high operating stability, and compatibility with fl exible substrates for OFETs. This report demonstrates a simple and low-cost means to make ultrathin low-k dielectrics by spin coating a polymer onto sputtered C nanoparticles (NPs), and it is a general method for various polymers and applicable to Therefore, the low-voltage operation can be realized for both the p-channel and n-channel, which implies a great potential of applying the present hybrid dielectrics to achieve lowpower organic complementary circuits.…”

“…First, the carrier trap density at the active-layer/dielectric interfaces should be low, so that the trapping-induced I DS instability is not prominent. Second, the low-k dielectrics possess relatively hydrophobic surfaces compared with commonly used SiO 2 dielectric and high-k polymer dielectrics such as polyvinylalcohol (PVA), [ 19 ] which may reduce water adsorption and thus hinder the water-induced I DS instability. Lastly, although the C NPs and PS/PVN containing aromatic groups may be capable of trapping charges, [ 19,26 ] V GS in the present case is too low to cause charge injection into the trapping sites.…”

“…Second, the low-k dielectrics possess relatively hydrophobic surfaces compared with commonly used SiO 2 dielectric and high-k polymer dielectrics such as polyvinylalcohol (PVA), [ 19 ] which may reduce water adsorption and thus hinder the water-induced I DS instability. Lastly, although the C NPs and PS/PVN containing aromatic groups may be capable of trapping charges, [ 19,26 ] V GS in the present case is too low to cause charge injection into the trapping sites. As a consequence, lowvoltage OFETs with high operating stability can be achieved upon adopting the dielectric structure of a low-k polymer onto the C NPs.…”

“…[12][13][14][15][16] However, the employment of a high-k dielectric could cause strong energetic disorder and thus enhanced carrier localization at the organic-active-layer/dielectric interface, which will reduce µ FE and the operating stability of the drain current ( I DS ). [17][18][19] Device performance can be greatly improved when an ultrathin low-k dielectric is used instead, whereas it may raise the issue of a large gate leakage current ( I GS ) due to a tiny d . Cross-linked polymer dielectrics have been developed to address the leakage issue, [ 13,14 ] which however need to optimize the cross-linking conditions for obtaining a smooth and homogeneous dielectric surface.…”

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

“…The C nano-floating-gate is well applied not only to the pentacene-based p-type OFETs but also to the N,N 0 -ditridecyl-3,4,9,10-perylenetetracarboxylic diimide (PTCDI-C 13 H 27 )-based n-type OFETs. 17 The memory device structure is schematically shown in Fig. 1, where heavily doped Si and 200-nm-thick SiO 2 on top (Silicon Quest, nþþ, 0.005 X cm) are used as the control-gate and control dielectric, respectively.…”