No abstract

both p-type and n-type OFETs. Based on the hybrid dielectrics, the operating gate bias ( V GS ) for the pentacene-based and N,N′ -ditridecyl-3,4,9,10-perylenetetracarboxylic diimide (PTCDI-C 13 H 27 )-based OFETs is down to −2 and 2 V, respectively. The devices exhibit typical µ FE , high ON/OFF ratio, and, in particular, excellent bias stress stability upon prolonged operation up to 6 × 10 4 s. The presence of the sputtered C NPs turns out to be the key for the formation of an ultrathin and pinhole-free polymer dielectric layer. This type of low-voltage OFETs with high operating stability can be realized on a fl exible substrate as well. Therefore, depositing an ultrathin low-k polymer on sputtered C NPs is a promising way for achieving high-performance low-voltage OFETs.The device structure of the low-voltage OFETs is schematically illustrated in Figure 1 , where a submonolayer of C is deposited by sputtering and spontaneously forms C NPs on Si. [ 23 ] The atomic force microscopy (AFM) image in Figure 1 demonstrates the uniform distribution of a number of C NPs on the substrate, and their height and lateral size are around 2 and 20 nm, respectively. The X-ray photoelectron spectroscopy (XPS) and Raman characterization results ( Figure S1, Supporting Information) suggest that the sputtered C NPs are amorphous C containing oxygenated groups and small graphite-like domains. [ 23 ] The C-NP-modifi ed Si surface possesses high surface energy and induces a small water contact angle of 45° (Figure 1 ), and the surface roughness is slightly increased from 0.17 ± 0.03 to 0.24 ± 0.03 nm upon the deposition of C NPs. Three kinds of low-k polymers, i.e., polystyrene (PS), polymethylmethacrylate (PMMA), and poly(2-vinyl naphthalene) (PVN), are then spin-coated onto the sputtered C NPs as the gate dielectrics (PS/C, PMMA/C, and PVN/C, respectively). The preparation conditions are controlled to deposit the dielectric layers as thin as 12-13 nm. Measured C i for the PS/C, PMMA/C, and PVN/C dielectrics ( Figure S2a,b, Supporting Information), about 180, 230, and 205 nF cm −2 , respectively, are quite large owing to their small d . Note that experimentally derived C i are well consistent with the theoretical ones calculated from k / d . For such ultrathin low-k dielectrics, the accumulated surface charge density ( n = C i V GS / q ) can be up to the order of 10 12 cm −2 at V GS = ±1 V, where q is the electron charge quantity. The pentacene/PTCDI-C 13 H 27 thin fi lm acts as the p-type/n-type organic active layer, respectively, and Cu on top is employed as the drain and source electrodes. [ 24 ] Figure 2 a-c shows the transfer characteristics of the pentacene-based low-voltage OFETs on the PS/C, PMMA/C, and PVN/C dielectrics, respectively, where the drain bias ( V DS ) is as low as −0.2 V and the V GS range is no higher than −2 V. I GS Organic fi eld-effect transistors (OFETs) are essential components in future fl exible, wearable, and portable electronic devices, which have numerous applications such as sensors, identifi cation ...

The MoO3/pentacene heterojunction is demonstrated to be effective for reducing the contact resistance in staggered organic thin-film transistors. The heterojunction-induced doping is nondestructive and may form a top conducting channel close to the pentacene surface. Contact interface doping and channel doping both significantly reduced the contact resistance. The effect of channel doping was prominent at low gate bias values, which is ascribed to the negligible access resistance owing to the presence of the top channel. Interface doping and channel doping were combined to obtain a complete heterojunction, which exhibited minimized contact resistance for a wide range of gate bias values.