Optical repeater circuit design based on InAlAs/InGaAs HEMT digital IC technology

Yoneyama, M.; Sano, Akira; Hagimoto, K.; Otsuji, T.; Murata, Koichi; Imai, Yasuhiko; Yamaguchi, S.; Enoki, T.; Sano, Eiichi

doi:10.1109/22.643831

Cited by 48 publications

(15 citation statements)

References 20 publications

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“…The 40-Gb/s interface circuit between an SFQ circuit at 4.2 K and a semiconductor circuit must amplify the voltage level from several hundreds microvolts for an SFQ pulse to 100 mV, which is the sensitivity of a decision circuit operating at 40 Gb/s made of InP high-electron mobility transistor (HEMT) [21]. The latching drivers with arrays of single Nb junction and YBCO junction supply 2.8-and 2.0-mV output, respectively.…”

Section: Structure Of Latching Driver and Output Interfacementioning

confidence: 99%

Output Interface With Latching Driver for LTS-SFQ Circuits

Hato

Horibe

Wakana

et al. 2005

IEEE Trans. Appl. Supercond.

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We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO -Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a of 45 kA/cm 2 , which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10 15 for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa 2 Cu 3 O 7 have an optimum of 60 kA/cm 2 that gives the smallest punchthrough probability lower than 10 15 for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum of 45 kA/cm 2 for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum is important to prepare 40-Gb/s SFQ systems. The of 60 kA/cm 2 is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.Index Terms-Interface circuit, latching driver, multichip module (MCM), punchthrough, single-flux quantum (SFQ).

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Section: Structure Of Latching Driver and Output Interfacementioning

confidence: 99%

Output Interface With Latching Driver for LTS-SFQ Circuits

Hato

Horibe

Wakana

et al. 2005

IEEE Trans. Appl. Supercond.

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“…1 These devices are used in preamplifiers, delayed flip flops, multiplexers, and clock and data recovery circuits. [2][3][4][5][6][7][8][9][10] Despite their attractive characteristics for high-speed operation, the channels of such devices cause impact ionization, which generates holes. These holes accumulate at the extrinsic source, causing kink phenomena [11][12][13][14][15] and drain conductance frequency dispersion.…”

Section: Introductionmentioning

confidence: 99%

NiAuGeAu ohmic contacts for a planar InP-based high electron mobility transistor structure with suppressed drain conductance frequency dispersion

Arai

Sawada

Hara

2003

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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We have fabricated a thermally stable low-contact-resistance Ni/AuGe/Au contact metal for InP-based high electron mobility transistors (HEMTs) without a heavily doped cap layer. The contact resistance is strongly influenced by the amount of Ni. Minimum contact resistance of 0.19 Ω mm was obtained from a Ni (1 nm)/AuGe (50 nm)/Au (99 nm) contact annealed at 300 °C for 5 min in N2. A smooth surface was obtained after contact formation and excellent thermal stability was achieved during isothermal annealing at 350 °C for 1 h in a N2 ambient. This alloyed ohmic contact satisfies the requirements for device fabrication process steps after the ohmic contact formation. It prevents hole accumulation by eliminating the hole barrier at the carrier-supply layer/channel interface. It also suppresses the kink phenomena and drain conductance frequency dispersion of InP-based HEMTs, and therefore will greatly facilitate the fabrication of ultrahigh-speed integrated circuits.

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“…This is significantly faster than the simulated oscillation frequency of the corresponding ring oscillator in BFL (f;,JrBFL = 2,14 GHz). The oscillation frequency is even more than 50 % higher than that of the DCFL ring-oscillator presented in [4] which reached an oscillation frequency of 2 GHz with a gate length of LG = 0.6 ym.…”

Section: N Measurementsmentioning

confidence: 76%

Section: Introductionmentioning

confidence: 99%

“…The gates are used for the implementation of multiplexer ICs operating up to 80 Gb/s [3]. Several other components such as demultiplexers, decision circuits and frequency dividers for 40 Gb/s data transmission systems have already been realized [4].Despite the technological difficulties, the integration of enhancement and depletion type HFETs for Direct Coupled FET Logic (DCFL) gates has been demonstrated [5]. Based on 0.5 pm gate-length transistors, an 1 l-stage ring oscillator with an oscillation frequency of about 2 GHz was produced [6].…”

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confidence: 99%

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An 11-stage ring oscillator with nonlinear negative feedback for high speed digital applications

Brennemann

Bushehri

Agethen³

et al.

Conference Proceedings. 2000 International Conference on Indium Phosphide and Related Materials (Cat. No.00CH37107)

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This paper presents the performance of an 1 l-stage ring oscillator for high speed digital circuits using a gate configuration with nonlinear negative feedback (NNFB). An additional transistor is introduced into the switching path of buffered FET logic (BFL) gate to reduce the logic HIGH level, thus limiting the logic swing.As the result, switching speed of the circuits is improved by about 50 % compared to conventional BFL gates, while maintaining almost the same power consumption. The performance of this logic design approach is demonstrated by an e-beam written 1 1 -stage ring-oscillator using InP-based depletion-type heterostructure field effect transistors (DHFET). The oscillation frequency is 3.36 GHz corresponding to a delay time of 13.5 ps per gate. I IntroductionIn high data rate communication, specifically in the field of fibre optic transmission, the InP based material system is of particular interest due to its unique ability to provide devices for transmitting and receiving optical signals in the 1.55 ym range as well as high speed electronic devices. Monolithic receivers with data rates above 20 Gb/s have already been realized in InP [l]. The next step is the implementation of digital circuits for further data processing, monolithically integrated with the front-end receiver itself [2].Due to the low Schottky-barrier of InAlAs lattice-matched to InP, the simultaneous fabrication of enhancement-and depletion-type HFETs requires highly sophisticated process technology. Therefore, Source Coupled FET Logic (SCFL) based on depletion-type HFETs is commonly applied. The gates are used for the implementation of multiplexer ICs operating up to 80 Gb/s [3]. Several other components such as demultiplexers, decision circuits and frequency dividers for 40 Gb/s data transmission systems have already been realized [4].Despite the technological difficulties, the integration of enhancement and depletion type HFETs for Direct Coupled FET Logic (DCFL) gates has been demonstrated [5]. Based on 0.5 pm gate-length transistors, an 1 l-stage ring oscillator with an oscillation frequency of about 2 GHz was produced [6].In this paper a logic gate configuration is presented using depletion mode InGaAs/InAlAs/InP HFETs (DHFET). A Nonlinear Negative Feedback (NNFB) has been implemented into the design of Buffered FET Logic (BFL) gates in order to achieve increased operating speed. This gate was simulated and optimized with respect to speed, then an Il-stage ringoscillator was fabricated in InP using the same layer stack as for the traveling wave amplifier of the optoelectronic receiver, provided in [ 11. The following sections of this paper describe the circuit design and performance evaluation of the NNFB gates and the technological realization of the ring oscillator. Finally, measurement results of the ring oscillator are shown demonstrating the feasibility of the gate for high speed data transmission applications. I1 Circuit Design Fig. 1.a shows the standard Buffered FET inverter using two supply voltages of VDD = 1.8 V and...

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Optical repeater circuit design based on InAlAs/InGaAs HEMT digital IC technology

Cited by 48 publications

References 20 publications

Output Interface With Latching Driver for LTS-SFQ Circuits

Output Interface With Latching Driver for LTS-SFQ Circuits

NiAuGeAu ohmic contacts for a planar InP-based high electron mobility transistor structure with suppressed drain conductance frequency dispersion

An 11-stage ring oscillator with nonlinear negative feedback for high speed digital applications

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