Optimal Bitwise Register Allocation Using Integer Linear Programming

Barik, Rajkishore; Grothoff, Christian; Gupta, Rahul; Pandit, Vinayaka; Udupa, Raghavendra

doi:10.1007/978-3-540-72521-3_20

Cited by 11 publications

(8 citation statements)

References 18 publications

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“…Combinatorial approaches to register allocation in isolation ( Table 1) have been proposed that satisfy all properties required to be practical: they model most or all of the standard program transformations (completeness, columns SP-MA), scale to medium-sized problems (scalability, column SZ), and generate executable code (executability, column EX). Furthermore, their ability to accommodate specific architectural features and alternative optimization objectives has been demonstrated in numerous studies [8,38,72,73]. A particular focus has been to study the trade-off between solution quality and scalability.…”

Section: Related Approachesmentioning

confidence: 99%

Combinatorial Register Allocation and Instruction Scheduling

Lozano

Carlsson

Blindell

et al. 2019

ACM Trans. Program. Lang. Syst.

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This paper introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice: it captures the complete set of program transformations used in state-of-the-art compilers, scales to mediumsized functions of up to 1000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain.An extensive evaluation confirms that Unison generates better code than LLVM while scaling to mediumsized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different processor architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1.1% to 10% and mean code size reduction ranges from 1.3% to 3.8% for the different architectures. A significant part of this improvement is due to the integrated nature of the approach. Executing the generated code on Hexagon confirms that the estimated speedup results in actual speedup. Given a fixed time limit, Unison solves optimally functions of up to 946 instructions, nearly an order of magnitude larger than previous approaches.The results show that our combinatorial approach can be applied in practice to trade compilation time for code quality beyond the usual compiler optimization levels, identify improvement opportunities in heuristic algorithms, and fully exploit processor-specific features. This paper is partially based on preliminary work presented at the Principles and Practice of Constraint Programming (2012) [20]; Languages, Compilers, and Tools for Embedded Systems (2014) [21]; and Compiler Construction (2016) [22] conferences. Compared to the preliminary work, this paper is completely restructured and rewritten, completes the combinatorial model with rematerialization, proposes extensions to capture additional program transformations and processor-specific features, and contributes a more exhaustive evaluation. Additions to the evaluation include more benchmarks and processors, evidence of the fundamental benefit of the integrated approach, an in-depth study of scalability, and actual execution measurements.

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Section: Related Approachesmentioning

confidence: 99%

Combinatorial Register Allocation and Instruction Scheduling

Lozano

Carlsson

Blindell

et al. 2019

ACM Trans. Program. Lang. Syst.

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“…Handling such processors can be seen as a generalization of register packing where register parts can be accessed with the finest granularity and the bit-width of temporaries varies through the program. The only combinatorial approach to bit-width aware register allocation is due to Barik et al [15]. Their key contribution is an IP register allocation model that allows multiple temporaries to be assigned to the same register r simultaneously as long as the bit capacity of r is not exceeded.…”

Section: Model Extensionsmentioning

confidence: 99%

Survey on Combinatorial Register Allocation and Instruction Scheduling

Lozano

Schulte

2019

ACM Comput. Surv.

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Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the past three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This article provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.

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“…It can also be used for bitwidth aware register allocation [Barik et al, 2006], branch prediction [Patterson, 1995] and synthesis of hardware for specic applications [Cong et al, 2005].…”

Section: Range Analysismentioning

confidence: 99%

Symbolic range analysis of pointers

Paisante

Maalej

Barbosa

et al. 2016

Proceedings of the 2016 International Symposium on Code Generation and Optimization

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Alias analysis is one of the most fundamental techniques that compilers use to optimize languages with pointers. However, in spite of all the attention that this topic has received, the current state-of-the-art approaches inside compilers still face challenges regarding precision and speed. In particular, pointer arithmetic, a key feature in C and C++, is yet to be handled satisfactorily. This work presents a new alias analysis algorithm to solve this problem. The key insight of our approach is to combine alias analysis with symbolic range analysis. This combination lets us disambiguate elds within arrays and structs, eectively achieving more precision than traditional algorithms. To validate our technique, we have implemented it on top of the LLVM compiler. Tests on a vast suite of benchmarks show that we can disambiguate several kinds of C idioms that current state-of-the-art analyses cannot deal with. In particular, we can disambiguate 1.35x more queries than the alias analysis currently available in LLVM. Furthermore, our analysis is very fast: we can go over one million assembly instructions in 10 seconds.

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Optimal Bitwise Register Allocation Using Integer Linear Programming

Cited by 11 publications

References 18 publications

Combinatorial Register Allocation and Instruction Scheduling

Combinatorial Register Allocation and Instruction Scheduling

Survey on Combinatorial Register Allocation and Instruction Scheduling

Symbolic range analysis of pointers

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