Optimal Circuits for Streamed Linear Permutations Using RAM

Optimum Circuits for Bit-Dimension Permutations

“…2) Proof of optimality: All the resulting permutations are serial-parallel or parallel-parallel. By including the costs in Table I in (27), the cost of the resulting permutation is…”

Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal

“…The permutation blocks in the figure have several stages with ss, or pp or sp permutations. The first approach consists of the composition of the permutations ss-pp-ss [7], the second approach is ppss-pp [5]- [9], the third approach is ss-sp [11] and the forth one is ss-pp-ss-pp [10].…”

“…Table III compares proposed and previous approaches to calculate the parallel bit reversal. Previous approaches that use memories are pp-ss-pp [5]- [9] or ss-pp-ss [7], whereas…”

“…By contrast, the proposed approach uses memories and ss-pp for N > P 2 , and pp-sp for N ≤ P 2 . Regarding delays/memory, previous approaches based on delays [10], [11] achieve the theoretical minimum, and some approaches based on memories [7]- [9] achieve a reasonable and slightly larger memory size of N . The proposed approach also requires a memory size of N .…”

“…Regarding multiplexers, some approaches [5], [8], [10] require a number of multiplexers proportional to P 2 . Other approaches [6], [7], [9] reduce the complexity to 2P log 2 P . Finally, only [7] and the proposed approach reduce the complexity to P log 2 P , whereas the complexity of [11] is in most cases larger, as it depends on N and N > P 2 .…”