Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

Ishiduki, Megumi; Fukuzumi, Y.; Katsumata, Ryoichi; Kito, M.; Kido, M.; Tanaka, Hidetake; Komori, Yosuke; Nagata, Yoshihiko; Fujiwara, Tomoko; Mutoh, T.; Mikajiri, Yoshimasa; Oota, Shigeto; Honda, Makoto; Iwata, Y.; Kirisawa, R.; Aochi, Hideaki; Nitayama, A.

doi:10.1109/iedm.2009.5424261

Cited by 66 publications

(35 citation statements)

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“…Finally, the photo overlay concerns in between the top SSL ), TCAT ), and VG (Kim et al 2009b;Lue et al 2010) , while VG may be scaled to 2X nm 5F 2 optimistically layout and hole further enlarge the cell size. A practical way of VC NAND is to design channel hole diameter (2 Â ONO + Si) in the range of 60-100 nm Jang et al 2009;Ishiduki et al 2009). Disregarding the practical processing concerns, in an optimal assumption, the ultimate scaling scenario of VC NAND may reach~4X nm 6F 2 cell size.…”

Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 98%

3D NAND Flash Architectures

Lue

2015

Charge-Trapping Non-Volatile Memories

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Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 98%

3D NAND Flash Architectures

Lue

2015

Charge-Trapping Non-Volatile Memories

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“…It has further been shown, that for the particular application the small dimensions enable the use of polycrystalline material for the transistor body [69]. This enables a rather simple fabrication technique where holes are etched into the layer stack and the holes are subsequently filled with polysilicon [30,70]. The basic process is illustrated in Fig.…”

Section: Electron Devices Based On Silicon Nanowiresmentioning

confidence: 98%

Silicon Nanowires: Fabrication and Applications

Mikolajick

Weber

2015

NanoScience and Technology

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Due to the high surface to volume silicon ratio and unique quasi onedimensional electronic structure, silicon nanowire based devices have properties that can outperform their traditional counterparts in many ways. To fabricate silicon nanowires, in principle there are a variety of different approaches. These can be classified into top-down and bottom-up methods. The choice of fabrication method is strongly linked to the target application. From an application point of view, electron devices based on silicon nanowires are a natural extension of the downscaling of a silicon metal insulator semiconductor transistor. However, the unique properties also allow implementing new device concepts like the junctionless transistor and new functionalities like reconfigurability on the device level. Sensor devices may benefit from the high surface to volume ratio leading to a very high sensitivity of the device. Also, solar cells and anodes in Li-ion batteries can be improved by exploiting the quasi one-dimensionality. This chapter will give a review on the state-of-the-art of silicon nanowire fabrication and their application in different types of devices.

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“…A major difference between the BiCS and the P-BiCS architectures is the placement of the SL plate. In the former architecture, the SL plate is placed on the bottom of the stack [10], whereas in the latter, it is placed on top. A low resistance SL plate is required to additionally increase the noise immunity along with the sensing characteristics of the memory.…”

Section: P-bics Architecturementioning

confidence: 99%

“…In the second category, we will provide the description of several architectures like: the Bit Cost Scalable (BiCS) presented for the first time by Toshiba [8,9], its improved version, namely the Pipe-shaped Bit Cost Scalable (P-BiCS) [10,11], and the pathway to the V-NAND architecture from Samsung [12,13] ranging from the Vertical Recess Array Transistor (VRAT) [14], the Vertical Stacked Array Transistor (VSAT) [15], and the Terabit Cell Array Transistor (TCAT) [16].…”

Section: Introductionmentioning

confidence: 99%

Architectural and Integration Options for 3D NAND Flash Memories

Micheloni

Crippa²,

Zambelli

et al. 2017

Computers

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Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. To keep the evolutionary pace of the technology, NAND Flash must scale aggressively in terms of bit cost. When approaching ultra-scaled technologies, planar NAND is hitting a wall: both academia researchers and industry worked to cope with this issue for several decades. Then, the 3D integration approach turned out to be the definitive alternative by eventually reaching mass production. This review paper exposes several 3D NAND Flash memory technologies, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features.

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Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

Cited by 66 publications

References 0 publications

3D NAND Flash Architectures

3D NAND Flash Architectures

Silicon Nanowires: Fabrication and Applications

Architectural and Integration Options for 3D NAND Flash Memories

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