Optimal dynamic range integrators

Groenewold, G.

doi:10.1109/81.168928

Cited by 66 publications

(26 citation statements)

References 15 publications

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“…Various differential integrator structures have previously been reported in the literature [2][3][4][5]. Some of them are implemented from classical operational amplifiers [2], others from operational transconducatance amplifiers (OTA's) [2][3][4]. However in practice, both suffer from feedback problems [2,4].…”

Section: Introductionmentioning

confidence: 99%

“…Some of them are implemented from classical operational amplifiers [2], others from operational transconducatance amplifiers (OTA's) [2][3][4]. However in practice, both suffer from feedback problems [2,4]. In addition, their frequency ranges of operation appear to be limited [5].…”

Section: Introductionmentioning

confidence: 99%

“…It is a dominant building block for many of active analog circuit design techniques and especially for state variable active filters [1]. Various differential integrator structures have previously been reported in the literature [2][3][4][5]. Some of them are implemented from classical operational amplifiers [2], others from operational transconducatance amplifiers (OTA's) [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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A New Balanced CMOS Controlled Integrator for Ultra High Frequency Applications

Zouaoui-Abouda

Fabre

2006

Analog Integr Circ Sig Process

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New implementations for single ended and balanced integrators using translinear mixed cells and operating in voltage mode are described. These integrators use the input translinear cell of a CMOS current controlled conveyor. The frequency ranges of correct operation of the compensated integrator are analyzed. It is shown that the high cut-off frequency now becomes located to the higher possible values. These integrators are designed and simulated using a 0.8 μm CMOS process. The frequency ranges of right operation of the compensated and uncompensated integrators are compared. They confirm very well the theory and underline the efficiency of the compensation methods.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New Balanced CMOS Controlled Integrator for Ultra High Frequency Applications

Zouaoui-Abouda

Fabre

2006

Analog Integr Circ Sig Process

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“…The situation regarding analog circuits is much more complicated and, as will be shown later, not so bright. The fundamental limits of power consumption in different types of analog circuits are discussed in several papers: switched capacitor filters in [20], continuous time filters in [21,22], and data converters in [23]. The common finding in these papers is that there is a certain energy needed to present the signal and the resulting power is proportional to the signal or clock frequency and the desired signal-to-noise ratio, but not dependent on the semiconductor devices used or the supply voltage.…”

Section: Chapter 2 Low Voltage Issuesmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…If the DR is fine, the sweep stops; if not then a new total capacitance value is taken and the loop is repeated. Formulas needed for scaling, capacitance distribution as well as the calculation of the DR are from [7]. The optimization does not alter the topology of the filter stages.…”

Section: Figure 2 Synthesis Workflow Of Actifmentioning

confidence: 99%