Optimal Gate Size Selection for Standard Cells in a Library

Abstract

Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area and low power, it is essential to have a good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) availablefor each of the primitives is an importantfactor to be considered. While an infinite granularity of gate sizes is preferable to get the best entitlement, it is often impractical due to the huge cost associated with developing and maintaining libraries. It is therefore essential to find ways to achieve the best performance, power and area, with a reasonable library size. In this paper we focus on the problem offinding out the optimal ratio of gate sizes to be selected. 65nm libraries were used for validating the claims on a real design and the results are presented in this paper.

Impact of range and precision in technology on cell-based design

“…This question is a stronger question than the library cell selection problem -if the suboptimality can be estimated, this procedure can be used to select a set of library cells, or even the technology that should be used to implement the design. In contrast, research on library cell selection [4,10,2] cannot estimate the suboptimality.…”