Optimal integrated code generation for clustered VLIW architectures

Keßler, Christoph; Bednarski, Andrzej

doi:10.1145/513829.513849

Cited by 14 publications

(3 citation statements)

References 9 publications

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“…Methods proposed in Lee and Chen (2004), Saghir et al (1996), Wang and Hu (2004), Zhuge et al (2001) solve both instruction scheduling and memory bank assignment problems, but do not consider the limitation of registers/accumulators. In addition, five methods (Cho et al, 2002;Kessler and Bednarski, 2002;Lee and Chen, 2005;Sudarsanam and Malik, 2000;Shiue, 2001) contain all above phases, and all except (Kessler and Bednarski, 2002) select Motorola DSP56000 as the target architecture. We describe three methods of them in some detail as follows.…”

Section: Related Workmentioning

confidence: 99%

An effective and efficient code generation algorithm for uniform loops on non-orthogonal DSP architecture

Lee

Chen

2007

Journal of Systems and Software

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Section: Related Workmentioning

confidence: 99%

An effective and efficient code generation algorithm for uniform loops on non-orthogonal DSP architecture

Lee

Chen

2007

Journal of Systems and Software

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“…The most closely related static (compiler) scheduling problem is the one posed by architectures such as partitioned VLIW [9,10,11,19,21,26] and RAW [14,25], which both consider register resource constraints and layout. Ozer et al solve the scheduling part of VLIW cluster assignment first with a later phase performing register assignment based on the cluster assignment of dependent instructions [19].…”

Section: Static Schedulingmentioning

confidence: 99%

A spatial path scheduling algorithm for EDGE architectures

Coons

Xia

Burger

et al. 2006

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems

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Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations -called anchor points -for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

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“…Partitioned VLIW: The SPDI scheduling problem bears the most resemblance to scheduling for a partitioned VLIW [15,17,20,23,25,35,10]. For RAW, which uses a 2-D VLIW execution model, the convergent scheduler handles complexity by computing an ALU preference for each scheduling heuristic [20].…”

Section: Related Workmentioning

confidence: 99%

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

Nagarajan¹,

Kushwaha²,

Burger³

et al.

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.

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Technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density will increase the number of execution units on a single chip, and decreasing wire transmission speeds will cause long and variable on-chip latencies. These trends will severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler instead work cooperatively, called Static Placement Dynamic Issue (SPDI). This paper focuses on the static instruction scheduler for SPDI. We identify and explore three issues SPDI schedulers must consider-locality, contention, and depth of speculation. We evaluate a range of SPDI scheduling algorithms executing on an Explicit Data Graph Execution (EDGE) architecture. We find that a surprisingly simple one achieves an average of 5.6 instructions-per-cycle (IPC) for SPEC2000 64-wide issue machine, and is within 80% of the performance without on-chip latencies. These results suggest that the compiler is effective at balancing on-chip latency and parallelism, and that the division of responsibilities between the compiler and the architecture is well suited to future systems.

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Optimal integrated code generation for clustered VLIW architectures

Cited by 14 publications

References 9 publications

An effective and efficient code generation algorithm for uniform loops on non-orthogonal DSP architecture

An effective and efficient code generation algorithm for uniform loops on non-orthogonal DSP architecture

A spatial path scheduling algorithm for EDGE architectures

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

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