Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

Abstract

Technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density will increase the number of execution units on a single chip, and decreasing wire transmission speeds will cause long and variable on-chip latencies. These trends will severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler instead work cooperatively, called Static Placement Dynamic Issue (SPDI). This paper focuses on the static instruction scheduler for SPDI. We identify and explore three issues SPDI schedulers must consider-locality, contention, and depth of speculation. We evaluate a range of SPDI scheduling algorithms executing on an Explicit Data Graph Execution (EDGE) architecture. We find that a surprisingly simple one achieves an average of 5.6 instructions-per-cycle (IPC) for SPEC2000 64-wide issue machine, and is within 80% of the performance without on-chip latencies. These results suggest that the compiler is effective at balancing on-chip latency and parallelism, and that the division of responsibilities between the compiler and the architecture is well suited to future systems.

A software-hardware hybrid steering mechanism for clustered microarchitectures

“…Software-based Mechanisms for Dynamically-scheduled Processors A very limited number of previous studies have proposed software-only mechanisms for dynamically-scheduled processors [14,19,26]. There are two advantages of using a software-only mechanism for clustered out-of-order processors.…”

“…Nagarajan et al [19] presented an execution model called static placement dynamic issue (SPDI) for Explicit Data Graph Execution (EDGE) architectures [4]. The EDGE architecture has similarities to a clustered out-of-order design.…”

“…Different software-only steering techniques have been proposed [14,19,26] and they are particularly common in statically-scheduled processors (e.g. VLIW) [6,13,8,12,16,17,21], where the compiler is responsible for both code scheduling and instruction distribution among clusters.…”

Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation

“…We first developed GRST, a GReedy list Scheduling for TRIPS [42]. Dissatisfied with its performance and based on preliminary experimental results with schedules produced by simulated annealing, we continued to improve the scheduler.…”

Critical path analysis of the TRIPS architecture

“…Further, in all possible executions, a block may execute at most 32 load/store instructions, and produce a constant number of outputs (stores, register writes, and one branch). The compiler also statically determines the placement for all instructions such that they map efficiently onto the microarchitecture [9]. The microarchitecture supports concurrent execution of up to eight blocks, seven of them speculatively.…”