Optimal Low Power Design of DDR2 Memory Interface for Compact Ultra Mobile Personal Computer (UMPC) Applications

Lee, J.B.; Ahn, Seungyoung; Yoon, S. D.; Chun, Jin Mi

doi:10.1109/eptc.2007.4469801

Cited by 2 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From the system cost point of view, using the wirebonding BOA package rather than the flip-chip BOA package, the 2-layer BOA package rather than the 4-layer BOA package, less routing area and components on the PCB, and cheap components, such as DDR2 SDRAM, can enhance the product competitiveness, but the system performance must be maintained. Some papers have been proposed on the DDR2 topology design or component optimization for power saving or cost reduction [1]- [4]. However, their applications are up to 800 Mb/s only.…”

Section: Introductionmentioning

confidence: 99%

Investigation of low cost consumer electronic system using 1066-Mb/s DDR2 interface design

Chen

Lin

2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

View full text Add to dashboard Cite

Memory-2 Memory-I TL3 Pkg Pkg TLO TLI Memory-I Memory-2 Pka TL2 Pkg TLI R T TL2 Pkg TL3 (a) TLO Pkg Controller Controller 2. DDR2 routing topology There are two types of command and control routing topology. Fig. I(a) shows DDR2 parallel terminated memory topology with R T and V TT (termination voltage, 0.9V). Fig. I(b) shows DDR2 series terminated memory topology. Routing the DDR2 command and control signals with series termination can achieve less layout area, power saving and cost saving for the de-coupling capacitors and termination regulator, such as LP2996 [5]. According to those benefits, the routing topology with the series termination with~is investigated if the DDR2 command and control performance can meet DDR2-1066 requirements. resistors and drive strengths. Finally, the optimized command and control routing topology without any damping resistor and termination voltage is achieved for DDR2 1066 Mb/s applications. (b) Figure I. DDR2 command and control routing topology for two ranks of xl6 SDRAMs in the 4-layer PCB. (a) Single parallel termination with R T and VTT. (b) Series termination with~. Transmission channel modelThe DDR2 SDRAM is encapsulated with a JEDEC standard package, a FBOA84 package [6]. The Ansoft Abstract Low cost is always the favorite feature of consumer electronics. The purpose of this paper is to study the possibility of low-cost design for DDR2-1066 memory interface. The S-parameters simulations of the PCB, DDR2 controller and SDRAM packages were performed using the electromagnetic field solvers up to 30Hz. Those broadband S-parameters were integrated with the chip SPICE models in the SPICE simulator for transient analyses. The results indicated that DDR2 command and control routing topology with zero series termination on the PCB and the controller using Level-7 drive strength encapsulated in the 2-layer PBOA package achieved 915-ps eye-aperture time, 507-ps signal skew, 2.14-V overshoot, and -0.37-V undershoot.

show abstract

Section: Introductionmentioning

confidence: 99%