Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs

Abstract

As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires grow rapidly, and have a significant impact on power consumption and signal integrity of an integrated circuit. As buses are major components of a design, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance. In this paper, we address the problem of using Hamming single error correcting code by optimizing both wire permutation and spacing. We propose an efficient polynomial time algorithm which applies graph theory for this optimization problem. Unlike previous studies [17], our approach can be applied to high bandwidth fault-tolerant buses to efficiently reduce the coupling capacitances by utilizing available space. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs for evaluating energy reduction. The results show that our approach can save energy up to 43% for the best case, and 30% for the worst with 20 × dmin (dmin is the mininal permitted wire distance) additional width on RLC model. Besides, we also provided comprehensive comparisons in experimental result section for different fault-tolerant bus layout methods and error correction codes.

Design and Analysis of Low Power Dynamic Bus Based on RLC simulation

“…Narayanan [10], Henkel [4] and Lv [8] lowered the power consumption dissipated by the self capacitance. Lin [7] and Ruan [11] only reduced capacitive effects between neighboring interconnect wires for low power. El-Moursy [2] and Li [6] optimized interconnect width to reduce inductive effects alone.…”