Optimal placement of vertical connections in 3D Network-on-Chip

Xu, Thomas Canhao; Schley, Gert; Liljeberg, Pasi; Radetzki, Marian; Plosila, Juha; Tenhunen, Hannu

doi:10.1016/j.sysarc.2013.05.002

Cited by 29 publications

(13 citation statements)

References 22 publications

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“…Based on the serialization methodology, Pasricha [36] proposed a 3D NoC synthesis framework; their approach adopt routers that have several local ports, which have high power consumption due to the increased number of ports and high data rates across the crossbar. On the other hand, existing inhomogeneous architectures (Figure 3a) [1,2,32,33,[37][38][39][40][41][42] do not consider the dynamics of application traffic load in their inhomogeneous architectures. Applications in such 3D NoCs are not optimized, as communication bandwidth and performance constraints of the applications were not considered in the architecture generation.…”

Section: D Network-on-chipmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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Abstract:To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs).

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Section: D Network-on-chipmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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“…1) [2], [22]- [25] however, do not consider the dynamics of application traffic load in their architectures generation. Applications in such 3D NoCs are not optimized as communication bandwidth and performance constraints of the applications were not considered in the architecture generation.…”

Section: A 3d Network-on-chip Architecturesmentioning

confidence: 99%

An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures

Agyeman

Zong

2016

2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)

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Abstract-To meet the performance and scalability demands of the fast-paced technological growth towards exascale and BigData processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-onChip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects tradeoff optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.

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“…11 We assume flit width of 128 bits, the same as in most studies. 15,16 Notice that in the destination cache coherent multicore processor system, the cache coherence protocol sends various types of messages for data reading/writing, as well as instruction fetching and maintaining shared data consistency. The messages are categorized as control and data messages, where control messages are no more than 64 bits, and data messages can be as long as 576 bits (a 64-bit control header plus a 512-bit full cache line).…”

Section: Related Workmentioning

confidence: 99%

“…The number of cores integrated in a chip multiprocessor is increasing constantly because of the requirement of parallel applications. 15,16 Notice that in the destination cache coherent multicore processor system, the cache coherence protocol sends various types of messages for data reading/writing, as well as instruction fetching and maintaining shared data consistency. 1 Manufactures are pushing mobile multicore processor with 10 cores.…”

Section: Introductionmentioning

confidence: 99%

PEN: a power law–enhanced network design for high efficiency multicore architecture

Leppänen

2016

Concurrency and Computation

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We propose a heterogeneous on-chip interconnection aiming at high efficiency multicore processors. An ideal on-chip interconnection should have low latency, high throughput, low power consumption, and high scalability. However, these metrics are usually contradictory with each other. Besides, a design should focus on the requirements of real applications. We investigate the characteristics of several parallel applications. It is found that the distribution of traffic is similar as the power law. We also discovered hot spot traffic, as well as bursty traffic from applications.Meanwhile, the average injection rate of parallel applications is relatively low. The proposed network is based on a dual-net concentrated mesh, where 2 physical networks are implemented for processing different messages and improve throughput. A diagonal interconnection is used in the central part of the network for alleviating the traffic hot spot without significant hardware overhead. We evaluate the proposed design with synthetic traffic and real applications by using a simulator. Results indicate that, on average for 8 applications, the network latency of the proposed design has reduced by 32% compared with regular mesh. Concerning efficiency when executing applications, the average energy delay product of the proposed design is 52.7% and 29.7% better than mesh and concentrate mesh, respectively.

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Optimal placement of vertical connections in 3D Network-on-Chip

Cited by 29 publications

References 22 publications

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures

PEN: a power law–enhanced network design for high efficiency multicore architecture

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