Optimal scheduling and software pipelining of repetitive signal flow graphs with delay line optimization

Abstract

Software pipelining can have an enormous impact on the clock cycle count and hence on the performance of a real-time signal processing design. Because it pays off to invest CPU time in the optimal software pipelining of time-critical parts of a design, an integer programming approach is proposed for simultaneous scheduling and software pipelining. The integer programming techniques in the literature do not support cyclic (repetitive) signalflow graphs, and/or do not allow optimization of the storage cost of delay lines during software pipelining. The new contributions in this paper are the full integration of software pipelining and scheduling, based on a new timing model that supports cyclic signal flow graphs and optimization of delay line storage costs. Experiments with several real-time signal processing applications have shown the practical applicability of the approach.

Retargetable Compilers for Embedded Core Processors

“…The concept is described in [9] using the S-DLX architecture, a super-scalar version of the well-known DLX architecture introduced by Hennessey and Patterson [43]. Loop folding [37] and pipelining concepts [21 ][47] are approaches used for pipelining DSP hardware architectures and are equally applicable to software.…”