Abstract. Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.

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Abstract:Keywords:In this paper, we address the design of a generic architecture for the management of residential services. The architecture consists of components both at the customers' side as well as at the service provider's side. The key features of the architecture are service modularity, the concept of service sessions, service packaging and subscription. The architecture allows service providers and telecom operators to rapidly provide new integrated value-added services to their customers. Layer-based design ensures that the architecture is independent of the particular service and service realization technology. The architecture provides generic access session management, service session mangement, subscription management and billing. Its implementation is based on J2EE (Java 2 Enterprise Edition). The various components of the architecture will be discussed, together with the implementation issues.

Software pipelining can have an enormous impact on the clock cycle count and hence on the performance of a real-time signal processing design. Because it pays off to invest CPU time in the optimal software pipelining of time-critical parts of a design, an integer programming approach is proposed for simultaneous scheduling and software pipelining. The integer programming techniques in the literature do not support cyclic (repetitive) signalflow graphs, and/or do not allow optimization of the storage cost of delay lines during software pipelining. The new contributions in this paper are the full integration of software pipelining and scheduling, based on a new timing model that supports cyclic signal flow graphs and optimization of delay line storage costs. Experiments with several real-time signal processing applications have shown the practical applicability of the approach.

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