Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Abstract

Reliability and the mean lifetime are major aspects in today's semiconductor device manufacturing. The continuous downscaling of transistor sizes and power supplies are the root causes of higher vulnerabilities of integrated circuits against time zero process variation, time dependent degradation and random faults induced by environmental influences like particle strikes. Handling permanent faults becomes inevitably a suitable solution to guarantee high reliabilities as well as increased lifetimes. Builtin self-repair is a possible solution, which exchanges faulty units with spare parts at the costs of extra hardware. In this paper, we evaluate the influence of different replacement strategies and their resulting additional hardware structures on reliability and mean lifetime. This analytical process allows to find the optimal replacement strategy for a given system, without implementing and synthesizing each case.

Generic built-in self-repair architectures for SoC logic cores

“…This is the main reason why only ad hoc methods exist in this area and the BISR architecture was introduced only for specific cores [5]- [7] and not as a generic architecture. Research was conducted to estimate the reliability of BISR architectures (considered again in the context of superscalar processors) [8]. The published estimation is based on the chip area occupied by BBs and switching elements (ratio to the chip area without backup is computed).…”

Repairing a 3-D Die-Stack Using Available Programmable Logic

“…One approach has been to use reconfigurable modules in FPGAs, such as logic blocks or routing resources, to replace the defective modules [15]. Another approach is to use spare functional units on FPGAs [16], such as spare ALUs [17]. These approaches implement both the original and spare modules on a single FPGA.…”