Optimal Zero-Voltage-Switching Method and Variable ON-Time Control for Predictive Boundary Conduction Mode Boost PFC Converter

Wang, Jizhe; Eto, Haruhi; Kurokawa, Fujio

doi:10.1109/tia.2019.2955431

Cited by 23 publications

(13 citation statements)

References 30 publications

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“…Boost converter inductor current ( ) and diode current ( ) can be expressed as (21) and (22) respectively.…”

Section: Design Of the Outer Voltage Loopmentioning

confidence: 99%

“…Substituting from (19, 20 and 21) in (22), the boost converter diode current ( ) complete equation can be written as (23).…”

Section: Design Of the Outer Voltage Loopmentioning

confidence: 99%

“…Another widely used technique to reduce the THD in PFC converters is the variable on-time (VOT) switching control technique by optimized the duty cycle of the PFC converter to decrease zero crossing distortion (ZCD) period [20][21][22][23], VOT switching control technique is reliable to reduce the THD in PFC converter but with complex mathematical analysis of the converter operation around the zero-crossing point in order to optimize the exact dead time around the zero-crossing point for exact on-time switching prediction [24]. This paper presents the small signal stability modeling of the conventional PFC boost converter proposed, and based on the signal stability model, an optimal integral-proportional (IP) current controller consists of double loop control strategy, where the integral gain feed forward to return the inductor current back to the reference set point, and the proportional gain implemented in the feedback path to increase the controller response.…”

Section: Introductionmentioning

confidence: 99%

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Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of High-Power Density PFC Boost Converter

Okilly¹,

Baek²

2020

Preprint

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This paper presents an optimal design for the inner current control loop of the continuous current conduction mode (CCM) power factor correction (PFC) stage, which it can be used as the front stage of the two stages alternating current-direct current (AC-DC) telecom power supply. Conventional single-phase CCM-PFC boost converter usually implemented with using of the proportional-integral (PI) controllers in both of the voltage and current control loops, to regulate the output DC voltage to the specified value, moreover to maintains the input current follows the input voltage which offers converter with high power factor (P.F) and low current total harmonic distortion (THD). However, due to the slow dynamic response of the PI controller at the zero-crossing point of the input supply current, input current can’t fully follow the input voltage which leads to high THD. Digitally controlled PFC converter with an optimal design of the inner current control loop using doubly control loops IP controller to reduce the THD and to offer input current with unity P.F was performed in this paper. Furthermore, for the economic design of the digitally control PFC converter, two isolated AC and DC voltage sensors are proposed and designed for the interfacing with the microcontroller unit (MCU). PSIM software was used to test the converter performance with using the proposed designed current controllers and isolated voltage sensors. High power density digitally controlled telecom PFC stage with P.F of about 99.93%, full load efficiency of about 98.70% and THD less 5.50% is achieved in this work.

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“…Boost converter inductor current ( ) and diode current ( ) can be expressed as (21) and (22) respectively.…”

Section: Design Of the Outer Voltage Loopmentioning

confidence: 99%

“…Substituting from (19, 20 and 21) in (22), the boost converter diode current ( ) complete equation can be written as (23).…”

Section: Design Of the Outer Voltage Loopmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of High-Power Density PFC Boost Converter

Okilly¹,

Baek²

2020

Preprint

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show abstract

“…Another widely used technique to reduce the THD in PFC converters is the variable ontime (VOT) switching control technique by optimizing the duty cycle of the PFC converter to decrease the zero-crossing distortion (ZCD) period [20][21][22][23]. The VOT switching control technique can reliably reduce the THD in PFC converters, but uses complex mathematical analysis of the converter operation around the zero-crossing point to optimize the exact dead time around the zero-crossing point for exact on-time switching prediction [24].…”

Section: Introductionmentioning

confidence: 99%

Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of a High-Power-Density PFC Boost Converter

2021

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This paper presents an optimal design for the inner current-control loop of the continuous current conduction mode (CCM) power factor correction (PFC) stage, which can be used as the front stage of the two-stage AC/DC telecom power supply. The conventional single-phase CCM-PFC boost converter is implemented with proportional–integral (PI) controllers in both the voltage and current-control loops to regulate the output DC voltage to the specified value and to ensure the input current follows the input voltage, which offers a converter with a high-power factor (PF) and low current total harmonic distortion (THD). However, due to the slow dynamic response of the PI controller at the zero-crossing point of the input supply current, the input current cannot fully follow the input voltage, which leads to high THD. In this paper, we investigate a digitally controlled PFC converter with an optimally designed inner current-control loop using a doubly-fed control loops integral-proportional (IP) controller to reduce the THD and to offer an input current with a unity PF. For the economic design of a digitally controlled PFC converter, two isolated AC and DC voltage sensors are designed for interfacing with the microcontroller unit (MCU). PSIM software as well as experimental prototype was used to test the converter performance using the proposed designed current controllers and isolated voltage sensors. We achieved a high-power-density, digitally controlled, telecom PFC stage with a power factor more than 99% and THD of about 5.50%.

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“…However, the nonlinear relationship with junction voltage makes it complex to intuitively understand the resonance behaviour of these parasitic capacitors. To simplify the resonant process, parasitic capacitors are considered as a constant value in a boost circuit based on GaN HEMT [16][17][18]. In order to evaluate a proper VS/ZVS time, it is necessary to discuss the resonant process with nonlinear capacitors in detail.…”

Section: Introductionmentioning

confidence: 99%

Extended Off-Time Control for CRM Boost Converter Based on Piecewise Equivalent Capacitance Model

et al. 2020

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Valley-switching (VS) and zero-voltage switching (ZVS) improves overall efficiency in critical conduction mode (CRM) boost converters. To achieve VS/ZVS, off-time of the main switch is often extended to match the resonance period by circuit inductor and parasitic capacitors of switching components. In this paper, a piecewise equivalent model for parasitic capacitors is proposed to derive analytical solutions of the resonant process, by which the numerical solutions of VS/ZVS time is calculated. To precisely achieve VS/ZVS in a boost converter, corresponding extended off-time based on the numerical solutions is implemented with an extended off-time (EOT) controller. The EOT controller makes the inductor volt-second unbalance in continuous conduction mode (CCM) operation during one switching cycle, leading to the convergence to CRM operation. The analytical and experimental results correct the results derived by conventional equivalent model for parasitic capacitors, which leads to deviated VS/ZVS boundary and wrongly calculated off-time. The proposed model and controller are verified in a nonsynchronous CRM boost converter based on GaN high electron mobility transistor (HEMT) and SiC diode. With the derived extended off-time, a peak efficiency of 99.15% is achieved at output power level of 200W. INDEX TERMS Critical conduction mode, parasitic capacitance, piecewise equivalent capacitance model, extended off-time control, boost converter.

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Optimal Zero-Voltage-Switching Method and Variable ON-Time Control for Predictive Boundary Conduction Mode Boost PFC Converter

Cited by 23 publications

References 30 publications

Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of High-Power Density PFC Boost Converter

Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of High-Power Density PFC Boost Converter

Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of a High-Power-Density PFC Boost Converter

Extended Off-Time Control for CRM Boost Converter Based on Piecewise Equivalent Capacitance Model

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