Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques

Abstract

Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these models in the future on HPC machines. In this paper we explore the optimisation of an existing, open source, FPGA based Credit Default Swap (CDS) engine using High Level Synthesis (HLS). Developed by Xilinx, and part of their open source Vitis libraries, the implementation of this engine currently favours flexibility and ease of integration over performance.We explore redesigning the engine to fully embrace the dataflow approach, ultimately resulting in an engine which is around eight times faster on an Alveo U280 FPGA than the original Xilinx library version. We then compare five of our engines on the U280 against a 24-core Xeon Platinum Cascade Lake CPU, outperforming the CPU by around 1.55 times, with the FPGA consuming 4.7 times less power and delivering around seven times the power efficiency of the CPU.

Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis

“…The Handle return data stage reads results from the AIE array and sends them to the other stage and also to the PL kernel. The second, Loopback Output: v1qe (data/output_v1qe.txt) _om_dma [8] _om_dma [7] _om_dma [6] _om_dma [2] _om_dma [1] _om_dma[0] _om_dma [5] _om_dma [4] _om_dma [ 2.…”

“…Falling within the broader domain of quantitative finance, which employs mathematical models and datasets to scrutinise financial markets, these workloads are computationally intensive and demand substantial computational resources. Although the prevailing approach is to execute these models on CPUs and GPUs, there have been several activities exploring the acceleration of quantitative finance on FPGAs [6][7][8].…”

Low-power option Greeks: Efficiency-driven market risk analysis using FPGAs

“…Nevertheless HLS is not a silver bullet, and whilst this technology has made the physical act of programming FPGAs much easier, one must still select appropriate kernels that will suit execution on FPGAs [4] and recast their Von Neumann style CPU algorithms into a dataflow style [12] to obtain best performance. Whilst there have been some successes in accelerating quantitative finance on FPGAs [8] [11] [9], and Xilinx have recently provided support in their open source Vitis Library [17] for numerous quantitative finance primitives, there is still much exploration to be undertaken especially with the objective of efficiency-driven computing looking to optimise both performance and energy efficiency. Furthermore, more development is needed of the underlying algorithmic techniques to inform software developers how best to port their codes to FPGAs.…”

“…Sitting under the broader field of quantitative finance, the use of mathematical models and datasets to analyse financial markets, such workloads are heavy users of computational resource. Whilst running these models on CPUs is currently dominant, there have been some successes with exploring the acceleration of quantitative finance using FPGAs [8] [11] [9]. However to date the majority use of FPGAs in the financial world has been in high-frequency trading.…”